公开(公告)号：US20230101045A1

公开(公告)日：2023-03-30

申请号：US17948616

申请日：2022-09-20

Applicant: Microchip Technology Incorporated

Inventor： Avinash Halageri ,  Sathya Narayanan

IPC: H04L1/00

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.

公开(公告)号：US12068854B2

公开(公告)日：2024-08-20

申请号：US17948616

申请日：2022-09-20

Applicant: Microchip Technology Incorporated

Inventor： Avinash Halageri ,  Sathya Narayanan

IPC: H04L1/00

CPC classification number: H04L1/0082 ,  H04L1/0041 ,  H04L1/0045

Abstract: A universal asynchronous receiver/transmitter includes a transmission register to include information to be transmitted, a receive register to include information received, a frame error checking circuit to evaluate contents of the receive register for a frame error, and control logic. The control logic is to route the contents of the transmission register to the receive register. The control logic is to, during transmission of the contents of the transmission register through the reprogrammable pin to the receive register, modify a bit inversion register to yield modified contents to be provided to the receive register. The modified contents are to cause a frame error. The control logic is to determine whether the frame error checking circuit detected the frame error.