公开(公告)号：US11188250B2

公开(公告)日：2021-11-30

申请号：US16171073

申请日：2018-10-25

Applicant: Micron Technology, Inc.

Inventor： David G. Springberg ,  David Sluiter

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

公开(公告)号：US20220083265A1

公开(公告)日：2022-03-17

申请号：US17537446

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： David G. Springberg ,  David Sluiter

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.

公开(公告)号：US11829638B2

公开(公告)日：2023-11-28

申请号：US17537446

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： David G. Springberg ,  David Sluiter

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/11 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0685 ,  G06F11/1068 ,  G06F12/0253 ,  G11C29/52 ,  H03M13/1102 ,  G06F2212/1044 ,  G06F2212/7205

Abstract: Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.