公开(公告)号：US20240176547A1

公开(公告)日：2024-05-30

申请号：US18432946

申请日：2024-02-05

Applicant: Micron Technology, Inc.

Inventor： Cagdas Dirik ,  Robert M. Walker ,  Elliott C. Cooper-Balis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/12

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/12

Abstract: An access tracker configured to receive a request to access a page, determine whether a page identification (ID) associated with the page is in the access tracker, increment an access count of the page in response to determining the page ID is in the access tracker, sort a number of page IDs based on an access count of each page ID, and determine whether a different page is hot or cold in response to sorting the number of page IDs.

公开(公告)号：US20230393770A1

公开(公告)日：2023-12-07

申请号：US17946518

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0679

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US11494119B2

公开(公告)日：2022-11-08

申请号：US17017396

申请日：2020-09-10

Applicant: Micron Technology, Inc.

Inventor： Elliott C. Cooper-Balis ,  Robert M. Walker ,  Paul Rosenfeld

IPC: G06F3/06

Abstract: An apparatus can include a memory device comprising a memory component and a memory controller that is coupled to the memory component. A memory searching component (MSC) is resident on the apparatus. The MSC can receive an external instruction indicative of performance of an operation to retrieve particular data from the memory component and issue, responsive to receipt of the instruction, a command to the memory controller to cause the memory controller to perform a read request invoking the memory component as part of performance of the operation in the absence of a further external instruction.

公开(公告)号：US12230311B2

公开(公告)日：2025-02-18

申请号：US17941655

申请日：2022-09-09

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Cagdas Dirik ,  Robert M. Walker ,  Sujeet Ayyapureddi ,  Niccolo Izzo ,  Markus Geiger ,  Yang Lu ,  Ameen Akel ,  Elliott C. Cooper-Balis ,  Danilo Caraccio

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/52

Abstract: An energy-efficient and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The reduction of the number of required counters is achieved by aliasing a plurality of rows that are being protected to each counter. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be DRAM.

公开(公告)号：US11281608B2

公开(公告)日：2022-03-22

申请号：US16058868

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  H01L23/538 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  H01L25/065 ,  H01L25/18

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20200210361A1

公开(公告)日：2020-07-02

申请号：US16815586

申请日：2020-03-11

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/1027 ,  G06F3/06 ,  H01L23/538 ,  G06F13/16 ,  G06F12/10

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20240411466A1

公开(公告)日：2024-12-12

申请号：US18808887

申请日：2024-08-19

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Sujeet Ayyapureddi ,  Edmund J. Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Robert M. Walker ,  Danilo Caraccio

IPC: G06F3/06

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

公开(公告)号：US11755515B2

公开(公告)日：2023-09-12

申请号：US17685212

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC classification number: G06F13/28 ,  G06F3/0659 ,  G06F3/0661 ,  G06F12/10 ,  G06F12/1027 ,  G06F13/1668 ,  H01L23/5385 ,  H01L23/5386 ,  G06F2212/65 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20220188253A1

公开(公告)日：2022-06-16

申请号：US17685212

申请日：2022-03-02

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F13/28 ,  G06F12/10 ,  H01L23/538 ,  G06F13/16 ,  G06F3/06 ,  G06F12/1027

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

公开(公告)号：US20190179769A1

公开(公告)日：2019-06-13

申请号：US16058868

申请日：2018-08-08

Applicant: Micron Technology, Inc.

Inventor： Brent Keeth ,  Richard C. Murphy ,  Elliott C. Cooper-Balis

IPC: G06F12/1027 ,  G06F3/06

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.