公开(公告)号：US08735292B2

公开(公告)日：2014-05-27

申请号：US13858800

申请日：2013-04-08

Applicant: Micron Technology, Inc.

Inventor： Junting Liu-Norrod ,  Er-Xuan Ping ,  Seiichi Takedai

IPC: H01L21/302

CPC classification number: H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Abstract translation: 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US20130237056A1

公开(公告)日：2013-09-12

申请号：US13858800

申请日：2013-04-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Junting Liu-Norrod ,  Er-Xuan Ping ,  Seiichi Takedai

IPC: H01L21/768

CPC classification number: H01L21/768 ,  C23C18/1605 ,  C25D5/022 ,  C25D7/12 ,  H01L21/56 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01028 ,  H01L2924/00

Abstract: Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Abstract translation: 一些实施方案包括其中绝缘材料同时沉积在半导体衬底的正面和跨衬底背面的方法。 随后，穿过前侧的绝缘材料可以蚀刻开口，然后可以将衬底浸入镀浴中，以在开口内增长导电接触区域。 跨越背面的绝缘材料可以在导电接触区域在前侧的生长期间保护背面免受电镀。 在一些实施例中，等离子体增强的原子层沉积可以用于沉积，并且可以在适于退火钝化材料的温度下进行，使得这种退火与等离子体增强的原子层沉积同时发生。

公开(公告)号：US10886130B2

公开(公告)日：2021-01-05

申请号：US16112410

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Darwin Franseda Fan ,  Junting Liu-Norrod ,  Michael Mutch

IPC: H01L21/76 ,  H01L21/20 ,  H01L21/02 ,  C23C16/56 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  C23C16/24 ,  C23C16/06 ,  H01L27/24

Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.

公开(公告)号：US20200066513A1

公开(公告)日：2020-02-27

申请号：US16112410

申请日：2018-08-24

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Darwin Franseda Fan ,  Junting Liu-Norrod ,  Michael Mutch

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  C23C16/24 ,  C23C16/06 ,  C23C16/56

Abstract: Some embodiments include a method of forming crystalline semiconductor material. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The deposition is conducted at a temperature of less than or equal to 500° C. Some embodiments include a method of forming a transistor. A template is provided to have a polycrystalline region along a surface. Semiconductor material is deposited along the surface under conditions which grow crystalline semiconductor structures from grains of the polycrystalline region. The semiconductor material includes germanium. The crystalline semiconductor structures are doped to form a configuration having a first portion over a second portion. Insulative material is formed adjacent the second portion. A transistor gate is formed along the insulative material.