公开(公告)号：US11442656B2

公开(公告)日：2022-09-13

申请号：US17182077

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

公开(公告)号：US20230393784A1

公开(公告)日：2023-12-07

申请号：US17832068

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Rohitkumar Makhija

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described are systems and methods for data path scheduling in memory systems. An example system comprises: a memory array comprising a plurality of memory cells; and a controller coupled to the memory array, the controller to perform operations comprising: retrieving a memory access command from a memory access command queue; identifying a memory device specified by the memory access command; verifying availability of the memory device; verifying availability of one or more resources that are required for servicing the memory access command; transmitting the memory access command to the memory device; and removing the memory access command from the memory access command queue.

公开(公告)号：US12271592B2

公开(公告)日：2025-04-08

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G11C13/00 ,  G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

公开(公告)号：US10929056B2

公开(公告)日：2021-02-23

申请号：US16235474

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.

公开(公告)号：US20210173585A1

公开(公告)日：2021-06-10

申请号：US17182077

申请日：2021-02-22

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: An indication that one or more program operations have been interrupted as a result of a read operation can be received at a first controller component associated with a memory sub-system. Context data associated with interrupted program operations can be received at the first controller component. A control sequence based on the context data can be generated at the first controller component. The control sequence can indicate how a second controller component associated with the memory sub-system interacts with a memory component of the memory sub-system to perform the read operation and to resume the interrupted program operations. The control sequence can further specify one or more additional operations that are associated with copying data of the interrupted program operations between first and second memory locations of the memory component. The control sequence can be provided to the second controller component.

公开(公告)号：US11803321B2

公开(公告)日：2023-10-31

申请号：US17943113

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method can include receiving, by a first controller component of a memory sub-system, a read operation, responsive to receiving the read operation, interrupting, by the first controller component, one or more program operations being performed by the memory sub-system, receiving, by the first controller component, a control sequence from a second controller component, wherein the control sequence is based on context data associated with the interrupted one or more program operations, and performing, by the first controller component, the control sequence by copying data of the interrupted one or more program operations from a first memory location to a second memory location of a memory component associated with the memory sub-system, and performing the read operation.

公开(公告)号：US20230059543A1

公开(公告)日：2023-02-23

申请号：US17887940

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Andrea Giovanni Xotta ,  Dheeraj Srinivasan ,  Ali Mohammadzadeh ,  Karl D. Schuh ,  Guido Luciano Rizzo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Tommaso Vali ,  Umberto Siciliani ,  Rohitkumar Makhija ,  June Lee ,  Aaron S. Yip ,  Daniel J. Hubbard

IPC: G06F3/06

Abstract: A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

公开(公告)号：US20200210098A1

公开(公告)日：2020-07-02

申请号：US16235474

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Horia C. Simionescu ,  Rohitkumar Makhija ,  Peng-Cheng Chen ,  Jung Sheng Hoei

IPC: G06F3/06

Abstract: A read operation can be received while one or more program operations are being performed at a memory sub-system. In response to receiving the read operation, the one or more program operations being performed at the memory sub-system can be interrupted. Context data associated with the one or more interrupted program operations can be determined and the context data can be provided to a firmware associated with the memory sub-system. A control sequence can be received from the firmware based on the context data. The read operation can be performed and the one or more interrupted program operations can be resumed based on the control sequence from the firmware.