公开(公告)号：US12086427B2

公开(公告)日：2024-09-10

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F1/28 ,  G06F1/08 ,  G06F3/06

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20230266890A1

公开(公告)日：2023-08-24

申请号：US17677641

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/28 ,  G06F1/08

CPC classification number: G06F3/0625 ,  G06F1/08 ,  G06F1/28 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US20250060875A1

公开(公告)日：2025-02-20

申请号：US18933971

申请日：2024-10-31

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Tawalin Opastrakoon

IPC: G06F3/06

Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.

公开(公告)号：US20240427507A1

公开(公告)日：2024-12-26

申请号：US18827515

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Fulvio Rori ,  Marco Domenico Tiburzi ,  Walter Di Francesco ,  Chiara Cerafogli ,  Tawalin Opastrakoon

IPC: G06F3/06 ,  G06F1/08 ,  G06F1/28

Abstract: Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

公开(公告)号：US12169629B2

公开(公告)日：2024-12-17

申请号：US18223933

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Tawalin Opastrakoon

IPC: G06F3/06

Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.

公开(公告)号：US20240069730A1

公开(公告)日：2024-02-29

申请号：US18223933

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Sriteja Yamparala ,  Tawalin Opastrakoon

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0673

Abstract: A method can include identifying one or more candidate memory blocks that are available for garbage collection, determining a respective erase depth level for each candidate memory block based on one or more block characteristics of the candidate memory block, erasing the candidate memory blocks, wherein each of the candidate memory blocks is erased in accordance with the respective erase depth level determined for the candidate memory block, receiving a request to write data subsequent to erasing the candidate memory blocks, and, responsive to receiving the request to write data, selecting a first memory block from the erased candidate memory blocks in accordance with the respective erase depth level of each of the erased candidate memory blocks. The block characteristics of the candidate memory block can include a program erase count and/or a temperature of the candidate memory block.