公开(公告)号：US20240393969A1

公开(公告)日：2024-11-28

申请号：US18662952

申请日：2024-05-13

Applicant: Micron Technology, Inc.

Inventor： Fanqi Wu ,  Kevin R. Brandt ,  Zhenlei Shen ,  Tingjun Xie ,  Yang Liu ,  Jiangli Zhu

IPC: G06F3/06

Abstract: A processing device in a memory sub-system determines a total power-off time of a memory sub-system and identifies a configurable power-off time threshold for the memory sub-system. The processing device determines whether the total power-off time satisfies a threshold criterion based on the configurable power-off time threshold, responsive to determining that the total power-off time satisfies the threshold criterion, causes the memory sub-system to enter a relaxed block retirement mode of operation.

公开(公告)号：US20240062839A1

公开(公告)日：2024-02-22

申请号：US17892437

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Seungjune Jeon ,  Yang Liu ,  Charles See Yeung Kwong

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3431 ,  G11C16/0483

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.

公开(公告)号：US20250078939A1

公开(公告)日：2025-03-06

申请号：US18771819

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Yang Liu ,  Steven Michael Kientz ,  Tingjun Xie ,  Aaron Lee ,  Jiangli Zhu ,  Wei Wang

IPC: G11C16/34 ,  G11C29/52

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals. Based on the scan result, two or the plurality of block families which are scanned within the same or different intervals can be combined and thus release block family memory if their measurement results satisfy combining criterion.

公开(公告)号：US20240347116A1

公开(公告)日：2024-10-17

申请号：US18755046

申请日：2024-06-26

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Seungjune Jeon ,  Yang Liu ,  Charles See Yeung Kwong

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3431 ,  G11C16/0483

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising identifying one or more valid pages of a first block, the first block being associated with a first management unit of the memory device; responsive to determining that a data integrity metric value associated with the first block satisfies a threshold criterion, causing the memory device to copy data from the one or more valid pages to a destination set of pages associated with a second block of a second management unit; marking each page of the one or more valid pages as invalid; and performing an error correcting operation, using one or more invalid pages of the first block, on a third block of the first management unit.

公开(公告)号：US20240069748A1

公开(公告)日：2024-02-29

申请号：US18219023

申请日：2023-07-06

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Yang Liu ,  Jiangli Zhu ,  Juane Li ,  Aaron Lee

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679

Abstract: A processing device in a memory sub-system performs a first media scan operation with respect to a plurality of memory pages addressable by the ordinary wordline, wherein each page of the plurality of memory pages is contained by a respective management unit, and responsive to determining that a value of a data state metric of a memory page of the plurality of memory page addressable by the ordinary wordline satisfies a specified condition, performs a first media management operation with respect to a management unit containing the memory page. The processing device further performs a second media scan operation with respect to a plurality of memory pages addressable by the mandatory wordline, wherein each page of the plurality of memory pages is contained by the respective management unit, and responsive to determining that a value of the data state metric of a memory page of the plurality of memory page addressable by the mandatory wordline satisfies the specified condition, performs a second media management operation with respect to the management unit containing the memory page.

公开(公告)号：US20250022529A1

公开(公告)日：2025-01-16

申请号：US18749234

申请日：2024-06-20

Applicant: Micron Technology, Inc.

Inventor： Fanqi Wu ,  Kevin R. Brandt ,  Zhenlei Shen ,  Tingjun Xie ,  Yang Liu ,  Jiangli Zhu

IPC: G11C29/44

Abstract: A processing device in a memory sub-system identifies a read error associated with a block and initiates a diagnostic memory access operation on the block. The processing device determines whether the diagnostic memory access operation was successfully performed on the block. Responsive to determining the diagnostic memory access operation was successfully performed on the block, the processing device initiates a diagnostic read operation on the block. The processing device determines whether the diagnostic read operation was successfully performed on the block. Responsive to determining the diagnostic read operation was successfully performed on the block, the processing device identifies the block as a healthy block.

公开(公告)号：US20240071462A1

公开(公告)日：2024-02-29

申请号：US18227139

申请日：2023-07-27

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Yang Liu ,  Juane Li ,  Aaron Lee ,  Jiangli Zhu

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/4096

Abstract: A processing device in a memory sub-system traverses a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit of the plurality of management units, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device. A non-transitory computer readable medium includes program instructions that when executed by a processing device, cause the processing device to perform operations of traversing a plurality of management units of a memory device at a defined scan/read refresh frequency. For every management unit, the processing device identifies a page satisfying a lowest sensing overhead criterion, and senses data of the identified page without transferring the data out of the memory device.

公开(公告)号：US20230195354A1

公开(公告)日：2023-06-22

申请号：US17579923

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Yang Liu ,  Zhongguang Xu ,  Murong Lang ,  Fangfang Zhu

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0614 ,  G06F3/0679

Abstract: One or more media scan parameters associated with a memory device are maintained. A number of program erase cycles associated with the memory device is identified. Responsive to determining that the number of program erase cycles satisfies a criterion, one or more adjusted media scan parameters are generated by adjusting the one or more media scan parameters. A media scan of the memory device is performed according to the one or more adjusted media scan parameters.

公开(公告)号：US12062401B2

公开(公告)日：2024-08-13

申请号：US17892437

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Seungjune Jeon ,  Yang Liu ,  Charles See Yeung Kwong

IPC: G11C16/04 ,  G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/0483

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.

公开(公告)号：US20240192875A1

公开(公告)日：2024-06-13

申请号：US18519611

申请日：2023-11-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yang Liu ,  Wenyen Chang ,  Wei Wang ,  Aaron Lee ,  Jiangli Zhu

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0679

Abstract: A system includes a memory device having a plurality of memory planes and a processing device operatively coupled with the memory device. The processing device to is perform operations including identifying a first block stripe of the memory device. The first block stripe includes a first plurality of blocks arranged across the plurality of memory planes. The operations further include determining that the first plurality of blocks of the first block stripe has greater than a threshold number of blocks associated with an error condition. Responsive to determining that the first plurality of blocks has greater than the threshold number of blocks associated with the error condition, the operations further include mapping a block of the first plurality of blocks associated with the error condition to a second block stripe including a second plurality of blocks having fewer than the threshold number of blocks associated with the error condition.