公开(公告)号：US12124365B2

公开(公告)日：2024-10-22

申请号：US17420210

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F13/1668 ,  G06F2212/401 ,  G06F2212/7201

Abstract: Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.

公开(公告)号：US12013742B2

公开(公告)日：2024-06-18

申请号：US17414300

申请日：2021-04-28

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F1/3234 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3287 ,  G06F1/3296

Abstract: Methods, systems, and devices for dynamic low power mode are described. An apparatus may include a memory device and a controller. The controller may receive a command to transition from a first power state to a second power state, the first power state associated with executing received command and the second power state associated with deactivating one or more components of the memory device. The controller may execute, while in the first power state, a set of operations associated with the transition from the first power state to second power state. The controller may determine whether a duration to execute the set of operations satisfies a delay duration between receiving the command and transitioning to the second power state from the first power state. The controller may transition from the first power state to the second power state based on determining whether the duration satisfies the delay duration.

公开(公告)号：US20250094338A1

公开(公告)日：2025-03-20

申请号：US18897773

申请日：2024-09-26

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F12/02 ,  G06F13/16

Abstract: Methods, systems, and devices for data organization for logical to physical table compression are described. The memory system may identify a region that includes one or more logical addresses associated with discontinuous corresponding physical addresses. The memory system may include a plurality of regions of logical addresses and a plurality of memory cells arranged according to a plurality of physical addresses. The memory system may determine a period of inactivity of access operations on the plurality of memory cells and rearrange, during the period of inactivity, information stored within the discontinuous corresponding physical addresses to be within continuous physical addresses of the plurality of physical addresses.

公开(公告)号：US20240264770A1

公开(公告)日：2024-08-08

申请号：US18423157

申请日：2024-01-25

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for tagging data based on chunk size are described. Generally, the described techniques provide for a device tagging data according to a chunk size of the data. The device may receive a command to write data. The command may include a first indication of a first type of the data (e.g., hot data, cold data). The device may determine whether a size of the data satisfies a threshold based on the command. The device may generate a second indication of a second type of the data based on whether the size of the data satisfies the threshold. The device may write the data to a buffer including a first set of blocks for storing the data in a first type of memory cells based on the second indication of the second type of the data (e.g., hot data, cold data).

公开(公告)号：US11886735B2

公开(公告)日：2024-01-30

申请号：US17701476

申请日：2022-03-22

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/10

Abstract: Methods, systems, and devices for data movement based on address table activity are described. A memory system may support a first type of data movement operation and a second type of data movement operation. The memory system may select between the first type of data movement operation and the second type of data movement operation for a region based on address table activity for the region.

公开(公告)号：US20240361949A1

公开(公告)日：2024-10-31

申请号：US18652604

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205

Abstract: Methods, systems, and devices for host initiated garbage collection are described. In some examples, a user accessible application or public interface of a host system may initiate a garbage collection procedure for a memory system using one or more vendor commands. For example, the host system and the memory system may support a first vendor command to check a fragmentation status or fragmentation parameter of the of the memory system. Additionally, the host system and the memory system may support a second vendor command to initiate a garbage collection procedure at the memory system, or to interrupt an ongoing garbage collection procedure. The host system and the memory system may also support a third vendor command to check the status of an initiated garbage collection procedure.

公开(公告)号：US20240281373A1

公开(公告)日：2024-08-22

申请号：US18441945

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F12/02 ,  G06F12/123

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F12/123

Abstract: Methods, systems, and devices for a memory system host data reset function are described. A reset operation may be performed to reset data in a memory system without erasing host data from the memory system. The memory system and a host system may perform the reset operation to sequentially reorder the data across pages and blocks of the memory system, mitigating holes in the data. The reset operation may enable sequentially reordering the data by performing refresh operations on the blocks and performing a subsequent garbage collection operation to consolidate the data within the pages of the refreshed blocks. The host system may reorganize the logical block addresses associated with the blocks and the memory system may perform the refresh operations and the garbage collection operations. The blocks may be refreshed according to an order of access frequency and according to a measure of performance impact on the memory system.

公开(公告)号：US11836077B2

公开(公告)日：2023-12-05

申请号：US17050237

申请日：2020-09-01

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0292 ,  G06F3/061 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamically tuning host performance booster thresholds are described. A memory system may include a set of memory devices and an interface configured to communicate commands with a host system coupled with the memory system. The interface may communicate commands to the memory system according to a first command mode associated with a logical address space including a plurality of regions and communicate commands according to a second command mode associated with physical memory address. The memory system may further include a controller that may determine a region activated for the second command mode, receive a first plurality of commands, determine, upon deactivating the region, a first threshold based on a first quantity of read commands serviced according to the second command mode. The controller may activate the region for the second command based on a second quantity of read commands received exceeding the first threshold.

公开(公告)号：US11604609B1

公开(公告)日：2023-03-14

申请号：US17497610

申请日：2021-10-08

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for command sequence adjustment are described. A memory system or a host system may adjust an order of a set commands in a queue if the memory system or host system determines that a subset of the commands in the queue are part of a test mode, for example by determining whether each command of the subset corresponds to a same size of data. The set of commands may be reordered such that the subset of commands associated with the test mode are continuous or back-to-back. In some cases, the subset of commands associated with test mode may be reordered such that logical addresses (e.g., logical block addresses) of the subset of commands are continuous.

公开(公告)号：US20230043338A1

公开(公告)日：2023-02-09

申请号：US17726101

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Yanhua Bi

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for memory zone size adjustment are described. A memory system may dynamically update the size of a stale zone configured to store data written during a write burst or write booster mode. The stale zone may be part of a first block of memory cells, and may retain data during a transfer operation, such as flush operation. The size of the stale zone may be updated in response to the memory system receiving a command, such as an unmap command. The size of the stale zone may be determined based on an available zone size, an amount of data indicated in the command, an amount of data indicated in the command that has been transferred to a second block of memory cells, or a combination thereof.