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公开(公告)号：US20230069439A1
公开(公告)日：2023-03-02
申请号：US17463274
申请日：2021-08-31
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yi-Min Lin , Fangfang Zhu , Chih-Kuo Kao
IPC: G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/42
Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
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公开(公告)号：US20240143231A1
公开(公告)日：2024-05-02
申请号：US18404999
申请日：2024-01-05
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Yi-Min Lin , Fangfang Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
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公开(公告)号：US11747994B2
公开(公告)日：2023-09-05
申请号：US17462335
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Chih-Kuo Kao , Yi-Min Lin
CPC classification number: G06F3/0619 , G06F1/30 , G06F3/0632 , G06F3/0653 , G06F3/0659 , G06F3/0679 , G06F11/3037
Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
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公开(公告)号：US11798614B2
公开(公告)日：2023-10-24
申请号：US17463274
申请日：2021-08-31
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yi-Min Lin , Fangfang Zhu , Chih-Kuo Kao
IPC: G11C11/4074 , G11C29/42 , G11C11/4096 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/42
Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
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公开(公告)号：US20230073518A1
公开(公告)日：2023-03-09
申请号：US17462335
申请日：2021-08-31
Applicant: Micron Technology, Inc.
Inventor： Chih-Kuo Kao , Yi-Min Lin
Abstract: A system can include multiple memory devices and a processing device that is operatively coupled with the memory devices as well as with a controller device, and a sequencer device, where the controller device is configured to perform operations. The operations can include, in response to receiving a potential power loss indication signal, receiving a power fault interrupt detection signal, as well as synchronizing the power fault interrupt detection signal. They can also include sending one or more memory access commands to the sequencer device. The operations can also include executing the one or more memory access commands on a medium and stopping transmission of commands based on a power loss handling setting while executing the commands.
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Patent Agency Ranking
公开(公告)号：US20250149079A1
公开(公告)日：2025-05-08
申请号：US19018182
申请日：2025-01-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yi-Min Lin , Fangfang Zhu , Chih-Kuo Kao
IPC: G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/42
Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords; and applies the first read voltage to a set of memory cells storing the one or more codewords.
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公开(公告)号：US12243577B2
公开(公告)日：2025-03-04
申请号：US18242155
申请日：2023-09-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yi-Min Lin , Fangfang Zhu , Chih-Kuo Kao
IPC: G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/42
Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
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公开(公告)号：US11880600B2
公开(公告)日：2024-01-23
申请号：US17446746
申请日：2021-09-02
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Yi-Min Lin , Fangfang Zhu
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
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公开(公告)号：US20230410878A1
公开(公告)日：2023-12-21
申请号：US18242155
申请日：2023-09-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yi-Min Lin , Fangfang Zhu , Chih-Kuo Kao
IPC: G11C11/4074 , G11C29/42 , G11C11/4096 , G11C11/4076
CPC classification number: G11C11/4074 , G11C29/42 , G11C11/4096 , G11C11/4076
Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
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公开(公告)号：US20230067281A1
公开(公告)日：2023-03-02
申请号：US17446746
申请日：2021-09-02
Applicant: Micron Technology, Inc.
Inventor： Ning Chen , Jiangli Zhu , Yi-Min Lin , Fangfang Zhu
IPC: G06F3/06
Abstract: A write request directed to the non-volatile memory device is received. A stripe associated with an address specified by the write request is present in the volatile memory device is determined. The volatile memory device includes a plurality of stripes, each stripe of the plurality of stripes having a plurality of managed units. The write request on a managed unit of the stripe in the volatile memory device is performed. The stripe in the volatile memory device is evicted to a stripe in the non-volatile memory device.
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