公开(公告)号：US11800635B2

公开(公告)日：2023-10-24

申请号：US17233200

申请日：2021-04-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Jyou Kikura ,  Toshihiro Tada ,  Tadashi Washimori

IPC: H01F27/28 ,  H01G4/008 ,  H01G4/12 ,  H01G4/33 ,  H05K1/02 ,  H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H01F27/2804 ,  H01G4/008 ,  H01G4/12 ,  H01G4/33 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/0792

Abstract: A capacitor is disposed on a substrate that is insulative. An inductor is disposed on the substrate. The inductor includes a conductor pattern having at least one end connected to the capacitor. The capacitor includes a dielectric film that mainly contains the same constituent element as a constituent element mainly contained in the substrate and at least two electrodes that face each other with the dielectric film interposed therebetween.

公开(公告)号：US11515442B2

公开(公告)日：2022-11-29

申请号：US17062461

申请日：2020-10-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Fujimoto ,  Koshi Himeda ,  Toshihiro Tada ,  Tetsuro Toritsuka ,  Shinji Kaburaki

IPC: H01L31/10 ,  H01S5/042 ,  H01S5/028 ,  H01S5/227

Abstract: An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer.

公开(公告)号：US20200152536A1

公开(公告)日：2020-05-14

申请号：US16744449

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.

公开(公告)号：US11380601B2

公开(公告)日：2022-07-05

申请号：US16744525

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L21/56 ,  H01L21/3205 ,  H01L23/367 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor chip is mounted on a substrate in a face-down manner. A metal film is arranged on a back surface of the semiconductor chip facing an opposite side from the substrate away from an edge of the back surface. A sealing resin layer seals the semiconductor chip with a part of the metal film being exposed from the sealing resin layer.

公开(公告)号：US11335617B2

公开(公告)日：2022-05-17

申请号：US16744449

申请日：2020-01-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hiroaki Tokuya ,  Yuichi Sano ,  Toshihiro Tada

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56

Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.