公开(公告)号：US09041154B2

公开(公告)日：2015-05-26

申请号：US13786463

申请日：2013-03-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chien-An Yu ,  Chih-Huang Wu

IPC: H01L29/00 ,  H01L27/04 ,  H01L23/522 ,  H01L27/06 ,  H01L27/108 ,  H01L49/02

CPC classification number: H01L27/04 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/91 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.

Abstract translation: 半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。 第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。 第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。 在存储器阵列区域中至少提供一个电容器结构。 电容器结构包括嵌入在第二电介质层中的电极材料层。 半导体存储器件还包括包括电极材料层的接触结构。

公开(公告)号：US20140252545A1

公开(公告)日：2014-09-11

申请号：US13786463

申请日：2013-03-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chien-An Yu ,  Chih-Huang Wu

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/91 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.

Abstract translation: 半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。 第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。 第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。 在存储器阵列区域中至少提供一个电容器结构。 电容器结构包括嵌入在第二电介质层中的电极材料层。 半导体存储器件还包括包括电极材料层的接触结构。