SILICON BURIED DIGIT LINE ACCESS DEVICE AND METHOD OF FORMING THE SAME
    2.
    发明申请
    SILICON BURIED DIGIT LINE ACCESS DEVICE AND METHOD OF FORMING THE SAME 有权
    硅掩模数字线路访问装置及其形成方法

    公开(公告)号:US20150123280A1

    公开(公告)日:2015-05-07

    申请号:US14069396

    申请日:2013-11-01

    Abstract: An access device includes a plurality of first digit lines (DL) trenches extending along a first direction, buried digit lines between each DL trench, second and third trenches separating the digit lines, a filling material filling the digit line trenches comprising airgaps in each second trench, a plurality of word line (WL) trenches extending along a second direction, metal word lines deposited on the walls of the word line trenches, a filling material filling the word line trenches.

    Abstract translation: 访问装置包括沿着第一方向延伸的多个第一数字线(DL)沟槽,每个DL沟槽之间的掩埋数字线,分隔数字线的第二和第三沟槽,填充数字线沟槽的填充材料,其包括在每一秒的气隙 沟槽,沿着第二方向延伸的多个字线(WL)沟槽,沉积在字线沟槽的壁上的金属字线,填充字线沟槽的填充材料。

    BURIED DIGITLINE (BDL) ACCESS DEVICE AND MEMORY ARRAY
    3.
    发明申请
    BURIED DIGITLINE (BDL) ACCESS DEVICE AND MEMORY ARRAY 有权
    BURIED DIGITLINE(BDL)访问设备和存储阵列

    公开(公告)号:US20140346652A1

    公开(公告)日:2014-11-27

    申请号:US13901592

    申请日:2013-05-24

    Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.

    Abstract translation: 存储器阵列包括沿着第一方向延伸的多个数字线(DL)沟槽; DL沟槽之间的埋置数字线; 密封每个DL沟槽中的气隙的沟槽填充材料层; 沿着第二方向延伸的多个字线(WL)沟槽; 设置在埋地数字线的一端的有源斩波(AC)沟槽; 气隙中的屏蔽层; 以及围绕AC沟槽的侧壁的侧壁导体。

    Buried digitline (BDL) access device and memory array
    4.
    发明授权
    Buried digitline (BDL) access device and memory array 有权
    埋地数字线(BDL)接入设备和存储器阵列

    公开(公告)号:US09070584B2

    公开(公告)日:2015-06-30

    申请号:US13901592

    申请日:2013-05-24

    Abstract: A memory array includes a plurality of digitline (DL) trenches extending along a first direction; a buried digitline between the DL trenches; a trench fill material layer sealing an air gap in each of the DL trenches; a plurality of wordline (WL) trenches extending along a second direction; an active chop (AC) trench disposed at one end of the buried digitline; a shield layer in the air gap; and a sidewall conductor around the sidewall of the AC trench.

    Abstract translation: 存储器阵列包括沿着第一方向延伸的多个数字线(DL)沟槽; DL沟槽之间的埋置数字线; 密封每个DL沟槽中的气隙的沟槽填充材料层; 沿着第二方向延伸的多个字线(WL)沟槽; 设置在埋地数字线一端的有源斩波(AC)沟槽; 气隙中的屏蔽层; 以及围绕AC沟槽的侧壁的侧壁导体。

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