公开(公告)号：US20190147936A1

公开(公告)日：2019-05-16

申请号：US15810122

申请日：2017-11-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C11/406 ,  G06F11/07

Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.

公开(公告)号：US20190115067A1

公开(公告)日：2019-04-18

申请号：US15782271

申请日：2017-10-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C11/406 ,  G11C11/4094 ,  G11C11/4074 ,  G11C29/50

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50008 ,  G11C29/74 ,  G11C2029/5004

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

公开(公告)号：US20190066760A1

公开(公告)日：2019-02-28

申请号：US15684384

申请日：2017-08-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C11/408 ,  G11C11/4076 ,  G11C11/4078 ,  G11C11/4091

Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array and a control device. The memory array has a plurality of word lines configured to control memory cells. The control device is configured to operate at least one word line of the word lines, derive an information on the operating of the at least word line, and cease maintaining data stored in the memory cells controlled by the at least one word line when the information satisfies a condition.

公开(公告)号：US20190122747A1

公开(公告)日：2019-04-25

申请号：US15790046

申请日：2017-10-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C29/00 ,  G11C5/14

Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.

公开(公告)号：US20190056874A1

公开(公告)日：2019-02-21

申请号：US15679148

申请日：2017-08-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G06F3/06 ,  G11C11/406

Abstract: Present disclosure relates to a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of word lines for storing data. The system comprises an accessing detector. The accessing detector is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing detector is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.

公开(公告)号：US20190115068A1

公开(公告)日：2019-04-18

申请号：US16201206

申请日：2018-11-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C11/406 ,  G11C11/4094 ,  G11C11/4074

CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/24 ,  G11C29/44 ,  G11C29/50 ,  G11C29/50008 ,  G11C29/74 ,  G11C2029/5004

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

公开(公告)号：US20190066765A1

公开(公告)日：2019-02-28

申请号：US15684524

申请日：2017-08-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/408

Abstract: The present disclosure provides a DRAM including a first refresh unit, a second refresh unit, and a control device. The first refresh unit has a first quantity of valid data. The second refresh unit has a second quantity of valid data less than the first quantity of valid data. The control device is configured to determine that the first refresh unit has a greater quantity of valid data than the second refresh unit, move valid data of the second refresh unit into the first refresh unit, and cease refreshing the second refresh unit whose valid data was moved into the first refresh unit.

公开(公告)号：US20190065079A1

公开(公告)日：2019-02-28

申请号：US15683793

申请日：2017-08-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chung-Hsun LEE ,  Hsien-Wen LIU

IPC: G06F3/06 ,  G06F11/20 ,  G06F11/14 ,  G06F11/16 ,  G06F11/10 ,  G06F1/24 ,  G11C11/22

CPC classification number: G06F3/0619 ,  G06F1/24 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1048 ,  G06F11/1441 ,  G06F11/1666 ,  G06F11/2015 ,  G11C11/2257

Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.