公开(公告)号：US20140264816A1

公开(公告)日：2014-09-18

申请号：US13797637

申请日：2013-03-12

Applicant: NVIDIA CORPORATION

Inventor： Shantanu Kalchuri ,  Brian Schieck ,  Abraham Yee

IPC: H01L23/34 ,  H01L21/50

CPC classification number: H01L23/4334 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

Abstract translation: 提供了涉及具有减小的厚度同时保持刚度的半导体封装结构的各种实施例。 在一个实施例中，半导体封装结构包括包括表面的衬底，包括连接到衬底的表面的第一界面的半导体管芯和与第一界面表面相对的第二界面表面，施加到衬底周围的模具化合物 半导体芯片。 半导体管芯的第二界面表面从模具化合物露出。 半导体封装结构包括附接到半导体管芯的第二界面的散热盖和模具化合物。

公开(公告)号：US10032692B2

公开(公告)日：2018-07-24

申请号：US13797637

申请日：2013-03-12

Applicant: NVIDIA Corporation

Inventor： Shantanu Kalchuri ,  Brian Schieck ,  Abraham Yee

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/433 ,  H01L25/16 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L23/31

Abstract: Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound.

公开(公告)号：US20150077918A1

公开(公告)日：2015-03-19

申请号：US14031714

申请日：2013-09-19

Applicant: Nvidia Corporation

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H05K1/14 ,  G06F1/18 ,  H05K3/30 ,  H05K1/02

CPC classification number: G06F1/183 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/2009 ,  Y10T29/4913 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

Abstract translation: 为具有基板的电子封装组件提供加强。 具有第一功能的第一电子封装通过设置在衬底第一表面的中心区域上的第一导电互连阵列机电地紧固到衬底的第一表面。 具有第二功能的第二电子封装件用第二导电互连阵列紧固到第一衬底表面。 至少一对第一阵列导体电耦合到至少一对第二阵列导体用于数据/信号交换，并且第一电子封装的至少一个部件与第二封装的至少一个部件相互作用。 金属加强环围绕至少基板的中心区域的外周设置。

公开(公告)号：US09760132B2

公开(公告)日：2017-09-12

申请号：US14031714

申请日：2013-09-19

Applicant: Nvidia Corporation

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/16 ,  G06F1/18 ,  H01L25/10 ,  H01L25/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: G06F1/183 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/2009 ,  Y10T29/4913 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

公开(公告)号：US20140124913A1

公开(公告)日：2014-05-08

申请号：US13668077

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/2009 ,  H01L2224/05599

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

Abstract translation: 提供了一种封装基板，封装半导体器件，计算装置及其形成方法。 在一个实施例中，提供了包括具有芯片安装表面和底面的封装结构的封装基板。 封装结构具有形成在芯片安装表面和底表面之间的多个导电路径。 导电路径被配置为在布置在芯片安装表面上的集成电路芯片和封装结构的底表面之间提供电连接。 包装结构具有接近包装结构的周边的芯片安装表面中形成的开口。 加强的微观结构设置在开口中并且联接到包装结构。

公开(公告)号：US09716051B2

公开(公告)日：2017-07-25

申请号：US13668077

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/495 ,  H01L23/52 ,  H01L23/31 ,  H01L23/42 ,  H01L23/00 ,  H05K1/02 ,  H01L23/498 ,  H05K3/46

CPC classification number: H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/2009 ,  H01L2224/05599

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.