公开(公告)号：US10102142B2

公开(公告)日：2018-10-16

申请号：US13727457

申请日：2012-12-26

Applicant: NVIDIA Corporation

Inventor： Guillermo J. Rozas ,  Bharath Krishnan ,  James Van Zoeren

IPC: G06F9/30 ,  G06F12/1027 ,  G06F9/38

Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

公开(公告)号：US20140181462A1

公开(公告)日：2014-06-26

申请号：US13727457

申请日：2012-12-26

Applicant: NVIDIA CORPORATION

Inventor： Guillermo J. Rozas ,  Bharath Krishnan ,  James Van Zoeren

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/3834

Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

Abstract translation: 一种用于检测CPU中指令排序违规的方法。 该方法包括：接收重新排序的指令流，并通过使用虚拟地址检测排序违规是否发生。 该方法还包括将重新排序的指令流的结果从加载存储缓冲器传送到高速缓存中，并通过使用物理地址检测是否发生了排序冲突。 随后，在检测到排序违规时启动恢复。