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    Virtual address based memory reordering
    2.
    发明授权
    Virtual address based memory reordering 有权

    公开(公告)号：US10102142B2

    公开(公告)日：2018-10-16

    申请号：US13727457

    申请日：2012-12-26

    Applicant: NVIDIA Corporation

    Inventor： Guillermo J. Rozas ,  Bharath Krishnan ,  James Van Zoeren

    IPC: G06F9/30 ,  G06F12/1027 ,  G06F9/38

    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

    DUAL-DOMAIN DYNAMIC MULTIPLEXER AND METHOD OF TRANSITIONING BETWEEN ASYNCHRONOUS VOLTAGE AND FREQUENCY DOMAINS
    4.
    发明申请
    DUAL-DOMAIN DYNAMIC MULTIPLEXER AND METHOD OF TRANSITIONING BETWEEN ASYNCHRONOUS VOLTAGE AND FREQUENCY DOMAINS 审中-公开
    双域动态多路复用器和异步电压与频域之间的转换方法

    公开(公告)号：US20140337659A1

    公开(公告)日：2014-11-13

    申请号：US13892931

    申请日：2013-05-13

    Applicant: Nvidia Corporation

    Inventor： Guillermo J. Rozas ,  Jason Golbus ,  Chi Keung Lee

    IPC: G06F1/08

    CPC classification number: G06F1/12

    Abstract: A dual-domain dynamic multiplexer and a method of transitioning between asynchronous voltage and frequency domains. One embodiment of the dual-domain dynamic multiplexer includes: (1) a first domain having a first voltage and a first clock, and a second domain having a second voltage and a second clock, (2) a plurality of data and data select input pairs wherein a data input of an input pair is in the first domain and a data select input of an input pair is in the second domain, and (3) a pre-charge stage in the second domain that is energized upon an edge of the second clock, whereby one data and data input pair is enabled and data latched in the second domain upon another edge of the second clock.

    Abstract translation: 双域动态多路复用器和在异步电压和频域之间转换的方法。 双域动态多路复用器的一个实施例包括：（1）具有第一电压和第一时钟的第一域，以及具有第二电压和第二时钟的第二域，（2）多个数据和数据选择输入 对，其中输入对的数据输入处于第一域，并且输入对的数据选择输入处于第二域，以及（3）第二域中的预充电阶段，其在 第二时钟，由此一个数据和数据输入对被使能，并且数据在第二时钟的另一边缘被锁存在第二域中。

    VIRTUAL ADDRESS BASED MEMORY REORDERING
    5.
    发明申请
    VIRTUAL ADDRESS BASED MEMORY REORDERING 审中-公开
    基于虚拟地址的内存重写

    公开(公告)号：US20140181462A1

    公开(公告)日：2014-06-26

    申请号：US13727457

    申请日：2012-12-26

    Applicant: NVIDIA CORPORATION

    Inventor： Guillermo J. Rozas ,  Bharath Krishnan ,  James Van Zoeren

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F9/3834

    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

    Abstract translation: 一种用于检测CPU中指令排序违规的方法。 该方法包括：接收重新排序的指令流，并通过使用虚拟地址检测排序违规是否发生。 该方法还包括将重新排序的指令流的结果从加载存储缓冲器传送到高速缓存中，并通过使用物理地址检测是否发生了排序冲突。 随后，在检测到排序违规时启动恢复。

    EXECUTION PIPELINE DATA FORWARDING
    8.
    发明申请
    EXECUTION PIPELINE DATA FORWARDING 有权
    执行管道数据转发

    公开(公告)号：US20140189316A1

    公开(公告)日：2014-07-03

    申请号：US13728765

    申请日：2012-12-27

    Applicant: NVIDIA CORPORATION

    Inventor： Gokul Govindu ,  Parag Gupta ,  Scott Pitkethly ,  Guillermo J. Rozas

    IPC: G06F9/30

    CPC classification number: G06F9/30079 ,  G06F9/3826 ,  G06F9/3834

    Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.

    Abstract translation: 在一个实施例中，在具有多个执行子单元的执行流水线中，提供使用旁路网络将数据从产生执行子单元直接转发到消耗执行子单元的方法。 该方法包括利用生产执行子单元产生输出数据，消耗与消耗执行子单元的输入数据，用于一个或多个中间操作，其输入是来自生产执行子单元的输出数据，其输出是输入数据到消费执行子单元 评估这些一个或多个介入操作以确定它们的执行是否构成识别功能，并且如果一个或多个中间操作将组成这样的身份功能，则控制旁路网络将产生执行子单元的输出数据直接转发到消费者 执行子单元。

    QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD
    10.
    发明申请
    QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD 有权
    在RUNAHEAD之后的QUEUED指令重新分配

    公开(公告)号：US20140189313A1

    公开(公告)日：2014-07-03

    申请号：US13730407

    申请日：2012-12-28

    Applicant: NVIDIA CORPORATION

    Inventor： Guillermo J. Rozas ,  Alexander Klaiber ,  James van Zoeren ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell D. Boggs ,  Magnus Ekman ,  Aravindh Baktha ,  David Dunn

    IPC: G06F9/30

    CPC classification number: G06F9/3814 ,  G06F9/3842 ,  G06F9/3863

    Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

    Abstract translation: 这里公开了微流器的各种实施例以及在径流操作期间操作微处理器的方法。 操作微处理器的一个示例性方法包括识别与跑步头触发指令相关联的跑跑前触发事件，并且响应于跑步头触发事件的识别，进入跑步头操作并将一个或多个附加指令连同插入跑步头触发指令 在队列中 示例性方法还包括响应于前导触发事件的解决恢复微处理器的非跑跑操作，以及将一个或多个附加指令与队列中的一个或多个附加指令重新分派到执行逻辑。

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