公开(公告)号：US09659815B2

公开(公告)日：2017-05-23

申请号：US14162696

申请日：2014-01-23

Applicant: NVIDIA Corporation

Inventor： Ronilo V. Boja ,  Teckgyu Kang ,  Abraham Fong Yee

IPC: H01L21/768 ,  H01L23/13 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76877 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

Abstract: A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of non-conductive material to expose the first set of pads, where the cavity is configured to contain the integrated circuit die oriented such that the second set of pads face the first set of pads.

公开(公告)号：US20140208590A1

公开(公告)日：2014-07-31

申请号：US13754799

申请日：2013-01-30

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ronilo V. Boja ,  Abraham Fong Yee ,  Zuhair Bokharey

IPC: H05K3/00

CPC classification number: H05K3/0094 ,  H05K3/0032 ,  H05K3/0047 ,  H05K3/42 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T29/49165

Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Abstract translation: 公开了一种用于制造在厚衬底中形成的具有高密度微孔的印刷电路板的方法。 该方法包括以下步骤：使用激光钻孔技术在厚基底中形成一个或多个孔，用导电材料电镀一个或多个孔，其中导电材料不完全填充一个或多个孔，并填充一个 或更多的电镀孔与非导电材料。

公开(公告)号：US10219387B2

公开(公告)日：2019-02-26

申请号：US13754799

申请日：2013-01-30

Applicant: NVIDIA Corporation

Inventor： Leilei Zhang ,  Ronilo V. Boja ,  Abraham Fong Yee ,  Zuhair Bokharey

IPC: H05K3/00 ,  H05K3/42

Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

公开(公告)号：US20150206848A1

公开(公告)日：2015-07-23

申请号：US14162696

申请日：2014-01-23

Applicant: NVIDIA Corporation

Inventor： Ronilo V. Boja ,  Teckgyu Kang ,  Abraham Fong Yee

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/76877 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

Abstract: A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of non-conductive material to expose the first set of pads, where the cavity is configured to contain the integrated circuit die oriented such that the second set of pads face the first set of pads.

Abstract translation: 提供了一种系统，方法和计算机程序产品，用于生产包装封装结构的腔体底部封装。 该方法包括以下步骤：接收包括衬底材料的底部封装，该衬底材料具有顶层，该顶层包括被配置为电耦合到集成电路管芯的第二组焊盘的第一组焊盘。 将不导电材料层施加到底部封装的顶层，并且在非导电材料层中形成空腔以露出第一组焊盘，其中空腔被配置为容纳集成电路裸片取向 使得第二组焊盘面向第一组焊盘。