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    Dynamic configuration of processing pipeline based on determined type of fetched instruction
    2.
    发明授权
    Dynamic configuration of processing pipeline based on determined type of fetched instruction 有权
    基于确定的获取指令类型的处理流水线的动态配置

    公开(公告)号：US09563432B2

    公开(公告)日：2017-02-07

    申请号：US13866914

    申请日：2013-04-19

    Applicant: NVIDIA Corporation

    Inventor： Ross Segelken ,  Darrell D. Boggs ,  Shiaoli Mendyke

    IPC: G06F9/30 ,  G06F15/76 ,  G06F9/38

    CPC classification number: G06F9/3873 ,  G06F9/30174

    Abstract: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided. In one embodiment, a micro-processing system includes a memory/storage subsystem configured to store non-native instruction set architecture (ISA) code and native ISA code in a common address space, fetch logic configured to retrieve the non-native ISA code and native ISA code from the common address space, instruction type determining logic configured to determine, at runtime, whether fetched instruction code is non-native ISA code or native ISA code, and processing logic configured to execute the fetched instruction code via a first pipeline configuration in response to the instruction type determining logic determining that the fetched instruction code is non-native ISA code, and via a second pipeline configuration which is different than the first pipeline configuration, in response to the instruction type determining logic determining that the fetched instruction code is native ISA code.

    Abstract translation: 提供了涉及在微处理系统中执行不同类型的指令代码的各种实施例。 在一个实施例中，微处理系统包括被配置为在公共地址空间中存储非本地指令集架构（ISA）代码和本地ISA代码的存储器/存储子系统，被配置为检索非本地ISA代码的提取逻辑， 来自公共地址空间的本地ISA代码，被配置为在运行时确定获取的指令代码是非本机ISA代码还是本地ISA代码的指令类型确定逻辑，以及经配置以经由第一流水线配置来执行所提取的指令代码的处理逻辑 响应于所述指令类型确定逻辑确定所提取的指令代码是非本地ISA代码，并且经由与所述第一流水线配置不同的第二流水线配置，响应于所述指令类型确定逻辑确定所述获取的指令代码 是本机ISA代码。

    QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD
    6.
    发明申请
    QUEUED INSTRUCTION RE-DISPATCH AFTER RUNAHEAD 有权
    在RUNAHEAD之后的QUEUED指令重新分配

    公开(公告)号：US20140189313A1

    公开(公告)日：2014-07-03

    申请号：US13730407

    申请日：2012-12-28

    Applicant: NVIDIA CORPORATION

    Inventor： Guillermo J. Rozas ,  Alexander Klaiber ,  James van Zoeren ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell D. Boggs ,  Magnus Ekman ,  Aravindh Baktha ,  David Dunn

    IPC: G06F9/30

    CPC classification number: G06F9/3814 ,  G06F9/3842 ,  G06F9/3863

    Abstract: Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to identification of the runahead-triggering event, entering runahead operation and inserting the runahead-triggering instruction along with one or more additional instructions in a queue. The example method also includes resuming non-runahead operation of the microprocessor in response to resolution of the runahead-triggering event and re-dispatching the runahead-triggering instruction along with the one or more additional instructions from the queue to the execution logic.

    Abstract translation: 这里公开了微流器的各种实施例以及在径流操作期间操作微处理器的方法。 操作微处理器的一个示例性方法包括识别与跑步头触发指令相关联的跑跑前触发事件，并且响应于跑步头触发事件的识别，进入跑步头操作并将一个或多个附加指令连同插入跑步头触发指令 在队列中 示例性方法还包括响应于前导触发事件的解决恢复微处理器的非跑跑操作，以及将一个或多个附加指令与队列中的一个或多个附加指令重新分派到执行逻辑。

    INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION
    7.
    发明申请
    INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION 审中-公开
    RUNAHEAD操作的指令分类

    公开(公告)号：US20140164738A1

    公开(公告)日：2014-06-12

    申请号：US13708544

    申请日：2012-12-07

    Applicant: NVIDIA CORPORATION

    Inventor： Magnus Ekman ,  Guillermo J. Rozas ,  Alexander Klaiber ,  James van Zoeren ,  Paul Serris ,  Brad Hoyt ,  Sridharan Ramakrishnan ,  Hens Vanderschoot ,  Ross Segelken ,  Darrell D. Boggs

    IPC: G06F9/30

    CPC classification number: G06F9/30 ,  G06F9/3842 ,  G06F9/3861

    Abstract: Embodiments related to methods and devices operative, in the event that execution of an instruction produces a runahead-triggering event, to cause a microprocessor to enter into and operate in a runahead without reissuing the instruction are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic for retrieving an instruction, scheduling logic for issuing the instruction retrieved by the fetch logic for execution, and runahead control logic. The example runahead control logic is operative, in the event that execution of the instruction as scheduled by the scheduling logic produces a runahead-triggering event, to cause the microprocessor to enter into and operate in a runahead mode without reissuing the instruction, and carry out runahead policies while the microprocessor is in the runahead mode that governs operation of the microprocessor and cause the microprocessor to operate differently than when not in the runahead mode.

    Abstract translation: 提供了与方法和设备相关的实施例，其中在指令的执行产生跑道前触发事件的情况下，提供微处理器进入并在没有重新发出指令的情况下操作。 在一个示例中，提供微处理器。 示例微处理器包括用于检索指令的提取逻辑，用于发出由执行提取逻辑检索的指令的调度逻辑以及前导控制逻辑。 示例性跑步头控制逻辑是可操作的，在由调度逻辑调度的指令的执行产生跑道前触发事件的情况下，使得微处理器进入并运行在跑步模式中而不重新发出指令，并执行 微处理器处于控制微处理器操作的跑头模式，并导致微处理器的操作与不在跑头模式时的运行不同。

    Fault detection in instruction translations
    8.
    发明授权
    Fault detection in instruction translations 有权

    公开(公告)号：US10324725B2

    公开(公告)日：2019-06-18

    申请号：US15915975

    申请日：2018-03-08

    Applicant: Nvidia Corporation

    Inventor： Nathan Tuck ,  David Dunn ,  Ross Segelken ,  Madhu Swarna

    IPC: G06F9/30 ,  G06F11/07

    Abstract: The disclosure provides a method and a system for identifying and replacing code translations that generate spurious fault events. In one embodiment the method includes executing a first set and a second set of native instructions, performing a third translation of a target instruction to form a third set of native instructions in response to a determination that a fault occurrence is attributed to a first translation, wherein the third set of native instructions is not the same as the second set of native instructions, and the third set of native instructions is not the same as the first set of native instructions, and executing the third set of native instructions.

    DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TYPE OF FETCHED INSTRUCTION
    10.
    发明申请
    DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TYPE OF FETCHED INSTRUCTION 有权
    基于确定类型的加工指令的加工管道动态配置

    公开(公告)号：US20140317382A1

    公开(公告)日：2014-10-23

    申请号：US13866914

    申请日：2013-04-19

    Applicant: NVIDIA CORPORATION

    Inventor： Ross Segelken ,  Darrell D. Boggs ,  Shiaoli Mendyke

    IPC: G06F9/30

    CPC classification number: G06F9/3873 ,  G06F9/30174

    Abstract: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided. In one embodiment, a micro-processing system includes a memory/storage subsystem configured to store non-native instruction set architecture (ISA) code and native ISA code in a common address space, fetch logic configured to retrieve the non-native ISA code and native ISA code from the common address space, instruction type determining logic configured to determine, at runtime, whether fetched instruction code is non-native ISA code or native ISA code, and processing logic configured to execute the fetched instruction code via a first pipeline configuration in response to the instruction type determining logic determining that the fetched instruction code is non-native ISA code, and via a second pipeline configuration which is different than the first pipeline configuration, in response to the instruction type determining logic determining that the fetched instruction code is native ISA code.

    Abstract translation: 提供了涉及在微处理系统中执行不同类型的指令代码的各种实施例。 在一个实施例中，微处理系统包括被配置为在公共地址空间中存储非本地指令集架构（ISA）代码和本地ISA代码的存储器/存储子系统，被配置为检索非本地ISA代码的提取逻辑， 来自公共地址空间的本地ISA代码，被配置为在运行时确定获取的指令代码是非本机ISA代码还是本地ISA代码的指令类型确定逻辑，以及经配置以经由第一流水线配置来执行所提取的指令代码的处理逻辑 响应于所述指令类型确定逻辑确定所提取的指令代码是非本地ISA代码，并且经由与所述第一流水线配置不同的第二流水线配置，响应于所述指令类型确定逻辑确定所提取的指令代码 是本机ISA代码。

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