公开(公告)号：US20240094291A1

公开(公告)日：2024-03-21

申请号：US17932808

申请日：2022-09-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Yilmaz ,  Vinod Pagalone ,  Munish Aggarwal ,  Doochul Shin

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318536 ,  G01R31/31727 ,  G01R31/318597

Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.

公开(公告)号：US11940493B1

公开(公告)日：2024-03-26

申请号：US17932808

申请日：2022-09-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Yilmaz ,  Vinod Pagalone ,  Munish Aggarwal ,  Doochul Shin

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/318536 ,  G01R31/31727 ,  G01R31/318597

Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.