公开(公告)号：US20210143824A1

公开(公告)日：2021-05-13

申请号：US16943529

申请日：2020-07-30

Applicant: NVIDIA Corp.

Inventor： Gaurawa Kumar ,  Ky-Anh Tran ,  Olakanmi Oluwole ,  Vishnu Balan

IPC: H03L7/08 ,  H04L25/497 ,  H04L25/03 ,  H04L25/49 ,  H04L25/06

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

公开(公告)号：US11184008B2

公开(公告)日：2021-11-23

申请号：US16943529

申请日：2020-07-30

Applicant: NVIDIA Corp.

Inventor： Gaurawa Kumar ,  Ky-Anh Tran ,  Olakanmi Oluwole ,  Vishnu Balan

IPC: H03D3/24 ,  H03L7/08 ,  H04L25/497 ,  H04L25/49 ,  H04L25/06 ,  H04L25/03

Abstract: This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

公开(公告)号：US10833681B1

公开(公告)日：2020-11-10

申请号：US16678979

申请日：2019-11-08

Applicant: NVIDIA Corp.

Inventor： Gaurawa Kumar ,  Ky-Anh Tran ,  Olakanmi Oluwole ,  Vishnu Balan

IPC: H03D3/24 ,  H03L7/08 ,  H04L25/03 ,  H04L25/497 ,  H04L25/49 ,  H04L25/06

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.