Clock Data Recovery Convergence In Modulated Partial Response Systems

    公开(公告)号:US20220311592A1

    公开(公告)日:2022-09-29

    申请号:US17379732

    申请日:2021-07-19

    Applicant: NVIDIA Corp.

    Abstract: A clock data recovery circuit detects illegal decisions for received data, accumulates a phase gradient for the data, determines a number of the illegal decisions in a configured window for receiving the data, and if the number of the illegal decisions exceeds a pre-defined number in the window, applies a sum of the accumulated phase gradient and a phase increment having a sign of the accumulated phase gradient to a clock circuit for the data receiver.

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