公开(公告)号：US20250123905A1

公开(公告)日：2025-04-17

申请号：US18488867

申请日：2023-10-17

Applicant: NVIDIA Corp.

Inventor： Sana Damani ,  Peter Nelson

IPC: G06F9/52 ,  G06T1/20 ,  G06T1/60

Abstract: A process to ameliorate scoreboard aliasing in multi-threaded data processors whereby, in response to executing at least one long-latency instruction in a first thread, a shared hardware scoreboard is incremented. A shared software register is incremented and the shared software register is spilled to a first per-thread register, and execution is switched to a second thread. After execution switches back to the first thread, execution of the first thread is suspended until the shared hardware scoreboard reaches a value at or below a difference between a value in the shared software register and the value spilled into the first per-thread register.