公开(公告)号：US11144087B2

公开(公告)日：2021-10-12

申请号：US16351319

申请日：2019-03-12

Applicant: NVIDIA Corp.

Inventor： Roger Allen ,  Alan Menezes ,  Tom Ogletree ,  Shounak Kamalapurkar ,  Abhijat Ranade

IPC: G06F1/12 ,  G06F9/48 ,  G06F9/38 ,  H04L12/26 ,  G06F9/30

Abstract: Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.

公开(公告)号：US20200050482A1

公开(公告)日：2020-02-13

申请号：US16351319

申请日：2019-03-12

Applicant: NVIDIA Corp.

Inventor： Roger Allen ,  Alan Menezes ,  Tom Ogletree ,  Shounak Kamalapurkar ,  Abhijat Ranade

IPC: G06F9/48 ,  H04L12/26 ,  G06F9/38

Abstract: Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.