公开(公告)号：US20230144553A1

公开(公告)日：2023-05-11

申请号：US17697325

申请日：2022-03-17

Applicant: NVIDIA Corp.

Inventor： Sana Damani ,  Sean Treichler ,  Mark Stephenson

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/48

CPC classification number: G06F9/30098 ,  G06F9/321 ,  G06F9/3009 ,  G06F9/4881 ,  G06F9/30065

Abstract: A computing system including one or more processor and one or more memory that stores application code that configures the processor to execute an application. The system includes logic to identify high and low register utilization regions of the application code and insert register acquire instructions and register release instructions in the application code by the compiler, such that when executed by the processor, the application code borrows and returns registers to an inter-block register pool when execution enters a high and low register utilization region, respectively.

公开(公告)号：US20230115044A1

公开(公告)日：2023-04-13

申请号：US17568514

申请日：2022-01-04

Applicant: NVIDIA Corp.

Inventor： Sana Damani ,  Sean Treichler ,  Mark Stephenson ,  Daniel Robert Johnson

IPC: G06F9/30 ,  G06F9/48

Abstract: Instruction set architecture extensions to configure priority ordering of divergent target branch instructions on SIMT computing platforms to enable tools such as compilers (e.g., under influence of execution profilers) or human software developers to configure branch direction prioritization explicitly in code. Extensions for simple (two-way) branch instructions as well as multi-target (more than two branch target instructions) are disclosed.