公开(公告)号：US20220107662A1

公开(公告)日：2022-04-07

申请号：US17405560

申请日：2021-08-18

Applicant: National Taiwan University of Science and Technology

Inventor： Hong-Wen Tsai ,  Yue-Feng Wu

IPC: G06F1/06 ,  H03F3/04 ,  H03K5/24 ,  G06N3/12

Abstract: A brain-computer interface device includes a plurality of pre-amplifiers are configured to amplify physiological signals corresponding to channels to output amplified signals; a multiplexer is configured to output, according to a control signal and a clock signal, the amplified signals; an analog-to-digital converter is configured to convert, according to the clock signal including clocks, the output of the multiplexer into a digital signal including a plurality of digital values corresponding to the clocks, wherein each of the digital values includes bit values; a memory is configured to store the digital signal; and a processor s configured to: add a header corresponding to one channel to each of the digital values according to the clock signal; and delete bit values of higher bits of each of the digital values corresponding to the same channel that are the same as those of a previous digital value, to output a compressed signal.

公开(公告)号：US11755058B2

公开(公告)日：2023-09-12

申请号：US17405560

申请日：2021-08-18

Applicant: National Taiwan University of Science and Technology

Inventor： Hong-Wen Tsai ,  Yue-Feng Wu

IPC: G06F1/06 ,  H03K5/24 ,  G06N3/12 ,  H03F3/04

CPC classification number: G06F1/06 ,  G06N3/12 ,  H03F3/04 ,  H03K5/24

Abstract: A brain-computer interface device includes a plurality of pre-amplifiers are configured to amplify physiological signals corresponding to channels to output amplified signals; a multiplexer is configured to output, according to a control signal and a clock signal, the amplified signals; an analog-to-digital converter is configured to convert, according to the clock signal including clocks, the output of the multiplexer into a digital signal including a plurality of digital values corresponding to the clocks, wherein each of the digital values includes bit values; a memory is configured to store the digital signal; and a processor s configured to: add a header corresponding to one channel to each of the digital values according to the clock signal; and delete bit values of higher bits of each of the digital values corresponding to the same channel that are the same as those of a previous digital value, to output a compressed signal.