公开(公告)号：US20230280937A1

公开(公告)日：2023-09-07

申请号：US18059966

申请日：2022-11-29

Applicant: Netlist, Inc.

Inventor： Jeekyoung Park ,  Jordan HORWICH

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635

Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output first strobe signals to accompany first data signals from the volatile memory subsystem during a memory read operation and to output second strobe signals together with second data signals carrying data from the non-volatile memory subsystem during a system-initiated NV read operation.

公开(公告)号：US11500797B2

公开(公告)日：2022-11-15

申请号：US17336262

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/0891

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

公开(公告)号：US12061562B2

公开(公告)日：2024-08-13

申请号：US18000125

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

IPC: G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/1642

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

公开(公告)号：US11513725B2

公开(公告)日：2022-11-29

申请号：US17023302

申请日：2020-09-16

Applicant: Netlist, Inc.

Inventor： Jeekyoung Park ,  Jordan Horwich

IPC: G06F3/06

Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

公开(公告)号：US20210081138A1

公开(公告)日：2021-03-18

申请号：US17023302

申请日：2020-09-16

Applicant: Netlist, Inc.

Inventor： Jeekyoung Park ,  Jordan HORWICH

IPC: G06F3/06

Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.

公开(公告)号：US12026397B2

公开(公告)日：2024-07-02

申请号：US18059966

申请日：2022-11-29

Applicant: Netlist, Inc.

Inventor： Jeekyoung Park ,  Jordan Horwich

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0683

Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output data strobe signals to accompany data from the volatile memory subsystem during a memory read operation and to output to accompany data strobes output by data buffers in response to data strobe signals from the memory controller during a system-initiated operation to transfer data from the NV memory subsystem to the volatile memory subsystem.