公开(公告)号：US11500797B2

公开(公告)日：2022-11-15

申请号：US17336262

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

IPC: G06F13/16 ,  G06F12/0862 ,  G06F12/0891

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

公开(公告)号：US12061562B2

公开(公告)日：2024-08-13

申请号：US18000125

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan Horwich ,  Jerry Alston ,  Chih-Cheh Chen ,  Patrick Lee ,  Scott Milton ,  Jeekyoung Park

IPC: G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/16

CPC classification number: G06F13/1673 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/1642

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.