公开(公告)号：US12182540B2

公开(公告)日：2024-12-31

申请号：US17626120

申请日：2020-02-20

Applicant: OMRON Corporation

Inventor： Yusaku Kobayashi ,  Daisuke Yagi

IPC: G06F9/44 ,  G05B19/05 ,  G06F8/30 ,  G06F9/445 ,  G06F9/455

Abstract: The present invention provides an information processing device, a recording medium, and a support system. With respect to a second program having a call instruction that designates an actual argument and calls a first program defined by using a dummy argument, the content of the first program defined by using the dummy argument according to a user operation is associated with the call instruction in the second program, and the associated result is displayed. In this case, the actual argument designated in the call instruction to the dummy argument is reflected in the first program, and the reflected result is displayed.

公开(公告)号：US11875065B2

公开(公告)日：2024-01-16

申请号：US17424367

申请日：2020-01-29

Applicant: OMRON Corporation

Inventor： Daisuke Yagi ,  Yusaku Kobayashi

IPC: G06F3/06

CPC classification number: G06F3/0683 ,  G06F3/0604 ,  G06F3/0655

Abstract: A control device includes a first controller, a second controller and a storage. The first controller performs safety control for a drive device. The second controller performs standard control for the drive device. The storage is accessible by both the first and second controllers and includes a first storage area and a second storage area. The first storage area stores data involved with the safety control, and the second storage area stores data involved with the standard control. The first controller accesses both the first storage area and the second storage area, and the second controller accesses the second storage area but is restricted from accessing the first storage area.

公开(公告)号：US12106103B2

公开(公告)日：2024-10-01

申请号：US17795780

申请日：2020-04-07

Applicant: OMRON CORPORATION

Inventor： Daisuke Yagi ,  Toru Murata ,  Atsushi Kamimura ,  Yasuo Muneta

IPC: G06F9/30 ,  G06F11/14 ,  G06F11/16

CPC classification number: G06F9/3004 ,  G06F11/1497 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/14 ,  G06F11/16

Abstract: An information processing device that executes an arithmetic process includes a first processing circuit and a second processing circuit. The first processing circuit executes the arithmetic process N times consecutively. The second processing circuit executes the arithmetic process N times consecutively. N is an integer of 2 or more. The first processing circuit and the second processing circuit continue to operate according to a match between at least one result among the results of the N arithmetic processes executed by the first processing circuit and at least one result among the results of the N arithmetic processes executed by the second processing circuit. As a result, it is possible to suppress an increase in cost required for hardware and to suppress a temporary stop due to a temporary failure.

公开(公告)号：US11054879B2

公开(公告)日：2021-07-06

申请号：US16641670

申请日：2018-10-02

Applicant: OMRON Corporation

Inventor： Keiichi Teranishi ,  Daisuke Yagi ,  Akihiro Yonezawa ,  Shotaro Koga

IPC: G06F1/3212 ,  G06F1/28

Abstract: The present invention achieves high speed safe response performance. A safety controller (100) includes a first voltage monitoring circuit (12) and a second voltage monitoring circuit (22). The first voltage monitoring circuit (12) is an AD converter which operates upon receiving electric power from a second electric power source (21) and which transmits, to a second MPU (20), a signal that gives notification of occurrence of an anomaly in a first voltage value. The second voltage monitoring circuit (22) is an AD converter which operates upon receiving electric power from a first electric power source (11) and which transmits, to a first MPU (10), a signal that gives notification of occurrence of an anomaly in a second voltage value.