Method for Producing an Optoelectronic Component, and Optoelectronic Component

    公开(公告)号:US20210336111A1

    公开(公告)日:2021-10-28

    申请号:US17366747

    申请日:2021-07-02

    Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer, applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer and wherein a proportion of the second metal in the seed layer is between 0.5 wt % and 10 wt %.

    Method for producing an optoelectronic component, and optoelectronic component

    公开(公告)号:US11094866B2

    公开(公告)日:2021-08-17

    申请号:US16495219

    申请日:2018-03-20

    Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a ratio of the first metal to the second metal in the seed layer is between 95:5 to 99:1.

    Optoelectronic component and method for producing an optoelectronic component

    公开(公告)号:US11621373B2

    公开(公告)日:2023-04-04

    申请号:US16635376

    申请日:2018-06-29

    Inventor: Guido Weiss

    Abstract: The invention relates to an optoelectronic device (100) comprising a semiconductor layer sequence (1) on a carrier (7), the semiconductor layer sequence (1) comprising at least one n-doped semiconductor layer (11), at least one p-doped semiconductor layer (12) and an active layer (13) sandwiched between the p- and n-doped semiconductor layers (11, 12), an reconnecting contact (2), which is configured for electrically contacting the n-doped semiconductor layer (11), a p-connecting contact (3), which is configured for electrically contacting the p-doped semiconductor layer (12), the n-connecting contact (2) being arranged on the side of the semiconductor layer sequence (1) facing away from the carrier (7), the n-connecting contact (2) having a first side (4) which is arranged facing the semiconductor layer sequence (1), wherein the first side (4) has two outer regions (43) and an inner region (44), viewed in lateral cross-section, which is delimited by the outer regions (43), wherein the outer regions (43) of the first side (4) are unstructured (42), and wherein the inner region (44) is structured (41).

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