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1.发明申请公开(公告)号：US20150362547A1
公开(公告)日：2015-12-17
申请号：US14304470
申请日：2014-06-13
Applicant: Oracle International Corporation
Inventor： Stephanie Moran , Michael C. Freda , Karl Sauter
CPC classification number: G01R31/2818 , G01B5/066 , G01B7/066 , G01B7/26 , G01R27/02 , H05K1/116 , H05K3/0047 , H05K2203/0207 , Y10T29/49156 , Y10T408/03
Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.
Abstract translation: 公开了一种用于PCB的步进钻探测试结构及其使用方法。 在一个实施例中，测试结构包括钻孔路径和连接通孔。 钻孔路径可以包括PCB的多个层中的选定的层上的感测垫（例如，非表面层）。 给定钻孔路径的传感垫可以是导电的，而钻孔路径的剩余部分是非导电的。 每个钻孔路径的感测垫可以电耦合到连接通孔。 在特定钻孔路径处的给定层的深度可以通过使用导电钻头钻入钻孔路径中并且确定何时在钻头和连接通孔之间进行电连接来确定。
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公开(公告)号：US09958496B2
公开(公告)日：2018-05-01
申请号：US14838605
申请日：2015-08-28
Applicant: Oracle International Corporation
Inventor： Stephanie Moran , Michael C. Freda , Karl Sauter
CPC classification number: G01R31/2813 , H05K1/0266 , H05K1/0268 , H05K1/0298 , H05K1/11 , H05K1/167 , H05K3/0052 , H05K3/0097 , H05K3/4679 , H05K2201/09381 , H05K2201/09636 , H05K2201/097 , H05K2201/09781 , H05K2203/166
Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB. A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.
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公开(公告)号：US20170059647A1
公开(公告)日：2017-03-02
申请号：US14838605
申请日：2015-08-28
Applicant: Oracle International Corporation
Inventor： Stephanie Moran , Michael C. Freda , Karl Sauter
CPC classification number: G01R31/2813 , H05K1/0266 , H05K1/0268 , H05K1/0298 , H05K1/11 , H05K1/167 , H05K3/0052 , H05K3/0097 , H05K3/4679 , H05K2201/09381 , H05K2201/09636 , H05K2201/097 , H05K2201/09781 , H05K2203/166
Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB.A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.
Abstract translation: 然后计算第一和第二电阻之间的差。 然后，基于该差异，确定沿着第一轴线的第一内层的配准距离（如果有的话）。
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公开(公告)号：US20160245857A1
公开(公告)日：2016-08-25
申请号：US15144206
申请日：2016-05-02
Applicant: Oracle International Corporation
Inventor： Stephanie Moran , Michael C. Freda , Karl Sauter
IPC: G01R31/28
CPC classification number: G01R31/2818 , G01B5/066 , G01B7/066 , G01B7/26 , G01R27/02 , H05K1/116 , H05K3/0047 , H05K2203/0207 , Y10T29/49156 , Y10T408/03
Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.
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