公开(公告)号：US20040140825A1

公开(公告)日：2004-07-22

申请号：US10737863

申请日：2003-12-18

Applicant: ORBOTECH, LTD.

Inventor： Dan Zemer ,  Eyal Harel

IPC: G01R031/02

CPC classification number: G01R31/2887 ,  G01R1/06705

Abstract: Apparatus for electrical testing of electrical circuits includes an array of probes arranged for selective engagement with portions of electrical circuits to be tested, testing circuitry associated with the array of probes for sensing electrical characteristics of the electrical circuits engaged by the array of probes, and control circuitry associated with the array of probes for causing engagement between selected ones of the array of probes with selected ones of the portions of electrical circuits to be tested. The array of probes includes at least two static probe assemblies arranged in a fixed array, and the static probe assemblies include a selectively positionable probe element and a probe element positioner. The apparatus is employed to test electrical circuits during fabrication.

公开(公告)号：US20020093650A1

公开(公告)日：2002-07-18

申请号：US10032060

申请日：2001-12-31

Applicant: Orbotech Ltd.

Inventor： Dan Zemer ,  Michael Faibisch

IPC: G01N021/88

CPC classification number: G01N21/88

Abstract: An optical inspection system has a topology sensing assembly. A height detector detects whether a region of a circuit has a height different from a height of the surface, and provides height data. A topology representation of the circuit, based on the height data, forms the basis for a reduced representation of the topology, and subsequent defect analysis.

Abstract translation: 光学检测系统具有拓扑感测组件。 高度检测器检测电路的区域是否具有与表面的高度不同的高度，并且提供高度数据。 基于高度数据的电路的拓扑表示形成了减少的拓扑表示和随后的缺陷分析的基础。

公开(公告)号：US20030020905A1

公开(公告)日：2003-01-30

申请号：US10032098

申请日：2001-12-31

Applicant: Orbotech Ltd.

Inventor： Nissim Savareigo ,  Igor Markov ,  Dan Zemer

IPC: G01N021/00

CPC classification number: G01N21/95684

Abstract: A first inspection functionality is provided to obtain information about a first attribute at a conductor location on an electrical circuit. A second inspection functionality is provided to obtain information about a second attribute at the conductor location. A combination of first attribute information and second attribute information is analyzed to determine an inspection attribute of the conductor at the conductor location. Attribute information may relate to one or more of: reflectance, fluorescence or height.

Abstract translation: 提供第一检查功能以获得关于电路上的导体位置处的第一属性的信息。 提供第二检查功能以获得关于导体位置处的第二属性的信息。 分析第一属性信息和第二属性信息的组合以确定导体位置处的导体的检查属性。 属性信息可以涉及以下中的一个或多个：反射率，荧光或高度。

公开(公告)号：US20020096555A1

公开(公告)日：2002-07-25

申请号：US09767645

申请日：2001-01-23

Applicant: ORBOTECH LTD.

Inventor： Scott Steven Waxler ,  Dan Zemer

IPC: B23K031/02 ,  B23K001/08

CPC classification number: B23K1/0056 ,  B23K2101/40 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00

Abstract: A system and method for forming bumps on an integrated circuit including a scanning direct laser imager employed to selectably expose a photosensitive layer deposited on an integrated circuit substrate, thereby to define regions overlying selected portions of the substrate, a developer developing said photosensitive layer to form apertures in the photosensitive layer at the defined regions, and a solder applicator applying a solder composition to the apertures to define solder bumps on the integrated circuit at selected portions thereof.

Abstract translation: 一种用于在包括扫描直接激光成像器的集成电路上形成凸块的系统和方法，所述扫描直接激光成像器用于可选择地曝光沉积在集成电路基板上的感光层，从而限定覆盖所述基板的选定部分的区域;显影所述感光层以形成 在限定区域的感光层中的孔，以及焊料施加器，将焊料组合物施加到孔，以在集成电路的选定部分处限定焊料凸块。

公开(公告)号：US20020013667A1

公开(公告)日：2002-01-31

申请号：US09906798

申请日：2001-07-18

Applicant: Orbotech, Ltd.

Inventor： Dan Zemer ,  Eyal Harel

IPC: G01R015/00

CPC classification number: G01R31/2887 ,  G01R1/06705

Abstract: Apparatus for electrical testing of electrical circuits includes an array of probes arranged for selective engagement with portions of electrical circuits to be tested, testing circuitry associated with the array of probes for sensing electrical characteristics of the electrical circuits engaged by the array of probes, and control circuitry associated with the array of probes for causing engagement between selected ones of the array of probes with selected ones of the portions of electrical circuits to be tested. The array of probes includes at least two static probe assemblies arranged in a fixed array, and the static probe assemblies include a selectively positionable probe element and a probe element positioner. The apparatus is employed to test electrical circuits during fabrication.

Abstract translation: 用于电气电气测试的装置包括一组探针，其布置用于与要测试的电路的部分选择性接合，与用于感测由探针阵列接合的电路的电特性的探头阵列相关联的测试电路，以及控制 与探针阵列相关联的电路，用于引起探针阵列中选定的探针阵列与要测试的电路部分中的选定部分之间的接合。 探针阵列包括以固定阵列布置的至少两个静态探针组件，并且静态探针组件包括可选择性定位的探针元件和探针元件定位器。 该装置用于在制造期间测试电路。