公开(公告)号：US10965438B1

公开(公告)日：2021-03-30

申请号：US16779666

申请日：2020-02-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Yang Sun ,  Sheng-Wen Chen ,  Yen-Po Lin ,  Bo-Jing Lin ,  Po-Min Cheng

IPC: H04L7/00 ,  H04L25/03 ,  H03L7/085 ,  H03L7/099

Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.

公开(公告)号：US11139816B2

公开(公告)日：2021-10-05

申请号：US16822025

申请日：2020-03-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Po-Min Cheng ,  Wun-Jian Su ,  Chia-Hui Yu

IPC: H04L7/00 ,  H03L7/08 ,  H03L7/085 ,  G06F1/10 ,  G06F1/08 ,  H03L7/107

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.

公开(公告)号：US20210273642A1

公开(公告)日：2021-09-02

申请号：US16822025

申请日：2020-03-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Po-Min Cheng ,  Wun-Jian Su ,  Chia-Hui Yu

IPC: H03L7/08 ,  H03L7/085 ,  H03L7/107 ,  G06F1/08 ,  G06F1/10

Abstract: A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.