-
1.发明申请MEMORY STORAGE DEVICE AND CONTROL METHOD THEREOF AND MEMORY CONTROL CIRCUIT UNIT AND MODULE 有权存储器件及其控制方法及存储器控制电路单元和模块公开(公告)号：US20160018997A1
公开(公告)日：2016-01-21
申请号：US14480643
申请日：2014-09-09
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiang-Hsiung Yu , Yuan-Cheng Chang , Wei-Cheng Wu
IPC: G06F3/06
CPC classification number: G06F13/1673
Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.
Abstract translation: 提供了包括第一和第二连接接口单元，存储器控制电路单元和接口电路的存储器存储设备。 第一连接接口单元和第二连接接口单元电连接到存储器控制电路单元的输入/输出通道。 接口电路设置在存储器控制电路单元和第一和第二连接接口单元中的至少一个之间。 接口电路被配置为提供至少一个主机系统与第一和第二连接接口单元中的至少一个之间的电连接配置的确定信息。 存储器控制电路单元被配置为基于确定信息向至少一个主机系统提供不同的操作功能。
-
2.发明授权公开(公告)号：US09760509B2
公开(公告)日：2017-09-12
申请号：US14480643
申请日：2014-09-09
Applicant: PHISON ELECTRONICS CORP.
Inventor： Hsiang-Hsiung Yu , Yuan-Cheng Chang , Wei-Cheng Wu
CPC classification number: G06F13/1673
Abstract: A memory storage device including a first and a second connection interface units, a memory control circuit unit and an interfacing circuit is provided. The first connection interface unit and the second connection interface unit are electrically connected to an input/output channel of the memory control circuit unit. The interfacing circuit is disposed between the memory control circuit unit and at least one of the first and the second connection interface units. The interfacing circuit is configured to provide determination information of an electrically connecting configuration between at least one host system and the at least one of the first and the second connection interface units. The memory control circuit unit is configured to provide different operation functions to the at least one host system based on the determination information.
-
Search Results
2
records
(took 0.012 seconds)
