公开(公告)号：US20240143207A1

公开(公告)日：2024-05-02

申请号：US17977934

申请日：2022-10-31

Applicant: Pure Storage, Inc.

Inventor： Sankara Vaideeswaran ,  Svitlana Tumanova ,  Ying Gao ,  Randy Zhao ,  Yuxuan Su

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0688

Abstract: A storage system is provided. The storage system includes a plurality of non-volatile memory modules a storage controller operatively coupled to the plurality of non-volatile memory modules, the storage controller comprising a processor. The process is to receive a set of data blocks to be stored in the plurality of non-volatile memory modules. The processor is further to program the set of data blocks at a first location of the plurality of non-volatile memory modules. The processor is further to determine whether a failure occurred while programming the set of data blocks in the plurality of non-volatile memory modules. The processor is further to reprogram a subset of the data blocks at a second location of the plurality of non-volatile memory modules, a number of blocks in the subset of data blocks based on durabilities of the set of data blocks, in response to determining that a failure occurred while programming the set of data blocks at the first location.

公开(公告)号：US20220300198A1

公开(公告)日：2022-09-22

申请号：US17832309

申请日：2022-06-03

Applicant: PURE STORAGE, INC.

Inventor： Ying Gao ,  Boris Feigin ,  Hari Kannan

IPC: G06F3/06

Abstract: A storage system has NVRAM (nonvolatile random-access memory), storage memory that includes SLC (single level cell) flash memory and QLC (quad level cell) flash memory, and a processor. The processor performs a method that includes determining that a size of a buffer of a storage system should be adjusted. The storage system comprises a non-volatile random-access memory (NVRAM), single level cell (SLC) flash memory, and quad level cell (QLC) flash memory. The buffer of the storage system comprises one or more of the NVRAM and a portion of the SLC flash memory. The method also includes adjusting the size of the buffer of the storage system to a first size.

公开(公告)号：US20220206702A1

公开(公告)日：2022-06-30

申请号：US17139460

申请日：2020-12-31

Applicant: PURE STORAGE, INC.

Inventor： Ying Gao ,  Boris Feigin ,  Hari Kannan ,  Igor Ostrovsky ,  Jeffrey Tofano

IPC: G06F3/06

Abstract: A storage system has a first memory, and a second memory that includes storage memory. The storage system has a processing device. The processing device is to select whether to write data to the first memory and write the data from the first memory to the second memory, or to write the data to the second memory bypassing the first memory. The processing device is to write portions of data for storage according to such selection.

公开(公告)号：US11847324B2

公开(公告)日：2023-12-19

申请号：US17512377

申请日：2021-10-27

Applicant: Pure Storage, Inc.

Inventor： Robert Lee ,  Boris Feigin ,  Ying Gao ,  Ronald Karr

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0644 ,  G06F3/0679

Abstract: A storage system establishes a staging region, for temporary writing of arriving data, and a stable region, for transfer of data from the staging region, in storage memory. The storage system establishes resiliency groups, each with a characteristic level of redundancy that is settable on an individual basis. The storage system performs data accesses of data stripes in accordance with the staging region, the stable region, a first resiliency group and a second resiliency group.

公开(公告)号：US20230342290A1

公开(公告)日：2023-10-26

申请号：US17726391

申请日：2022-04-21

Applicant: Pure Storage, Inc.

Inventor： Svitlana Tumanova ,  Richard Troxell, III ,  Ying Gao

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/023 ,  G06F13/1668 ,  G06F2212/1041

Abstract: A die-aware scheduler that has a hierarchical queue is suitable for use in data storage systems. The hierarchical queue includes a priority queue, a die queue, a write queue and a power token queue, and may also include an admission queue. The die queue, the write queue and the power token queue have a width and lanes corresponding to dies in solid-state storage. The hierarchy of queues has dynamic adjustability of a ratio relating to handling queue items in the hierarchy of queues, to optimize latency and throughput.

公开(公告)号：US11614893B2

公开(公告)日：2023-03-28

申请号：US17159796

申请日：2021-01-27

Applicant: PURE STORAGE, INC.

Inventor： Hari Kannan ,  Boris Feigin ,  Ying Gao ,  John Colgrove

IPC: G06F3/06 ,  G06F11/07 ,  G06F11/10 ,  G06F11/34 ,  G06F12/0804 ,  G06F12/0866 ,  G06F11/30

Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.

公开(公告)号：US20220206696A1

公开(公告)日：2022-06-30

申请号：US17570340

申请日：2022-01-06

Applicant: PURE STORAGE, INC.

Inventor： Ying Gao ,  Boris Feigin ,  Hari Kannan ,  Igor Ostrovsky ,  Jeffrey Tofano ,  Svitlana Tumanova

IPC: G06F3/06

Abstract: A storage system has a first memory, a second memory that include solid-state storage memory, and a processing device. The processing device is to select a mode for each portion of data to be written. Selection of the mode is based at least on size of the portion of data. Selection of the mode is from among modes that include a first mode of writing the portion of data in mirrored RAID form to the first memory for later transfer from the first memory to the second memory, a second mode of writing the portion of data in parity-based RAID form to the first memory for later transfer from the first memory to the second memory, and a third mode of writing the portion of data to the second memory, bypassing the first memory. The processing device is to handle portions of data to be written according to such selection.

公开(公告)号：US20220156152A1

公开(公告)日：2022-05-19

申请号：US17581340

申请日：2022-01-21

Applicant: PURE STORAGE, INC.

Inventor： Ying Gao ,  Hari Kannan ,  Boris Feigin ,  Robert Lee

IPC: G06F11/10 ,  G06F3/06

Abstract: A storage system determines a size of a portion of data to be written as a RAID stripe across storage devices. The storage system determines aspects of the RAID stripe. Aspects of the RAID stripe include a data segment size for shards of the RAID stripe, a type of RAID, a width of the RAID stripe, a level of redundancy of the RAID stripe, and a selection of members of the storage devices. All of the determining for the aspects of the RAID stripe are on a dynamic basis and based at least on the size of the portion of data. The storage system writes the portion of data according to the determined aspects of the RAID stripe across the selected members of the storage devices.

公开(公告)号：US20210349649A1

公开(公告)日：2021-11-11

申请号：US17379762

申请日：2021-07-19

Applicant: Pure Storage, Inc.

Inventor： Robert Lee ,  Boris Feigin ,  Ying Gao ,  Ronald Karr

IPC: G06F3/06

Abstract: A method of operating a storage system, and related storage system, are provided. The storage system establishes resiliency groups, each having a defined level of redundancy of resources of the storage system. The resiliency groups include at least one compute resources resiliency group and at least one storage resources resiliency group. The storage system supports capability of configurations that have multiples of each of the resiliency groups. Blades of the storage system perform distributed data and metadata storage across modular storage devices, in accordance with the resiliency groups.

公开(公告)号：US20210182190A1

公开(公告)日：2021-06-17

申请号：US17159986

申请日：2021-01-27

Applicant: Pure Storage, Inc.

Inventor： Ying Gao ,  Boris Feigin ,  Hari Kannan

IPC: G06F12/02

Abstract: A scheduling system for a memory controller is provided. The system includes operation queues and a scheduler. The scheduler receives operation requests, prioritizes each operation request according to one or more policies, and inserts each operation request into an operation queue.