公开(公告)号：US20220328422A1

公开(公告)日：2022-10-13

申请号：US17454742

申请日：2021-11-12

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG CHIEN ,  Nan-Chun LIN ,  Hung-Hsin HSU

IPC: H01L23/552 ,  H01Q1/22 ,  H01L23/66 ,  H01L21/56 ,  H01L21/762

Abstract: A fan-out semiconductor package includes: a redistribution structure; a functional chip coupled to the redistribution structure; an isolation structure disposed on the redistribution structure and including a body formed with through-holes; a shielding structure disposed on the isolation structure and the redistribution structure; a first conductive pattern structure disposed on the isolation structure and extending through the through-holes of the isolation structure; an encapsulating structure disposed on the isolation structure, the shielding structure and the first conductive pattern structure; and a second conductive pattern structure disposed on the encapsulating structure. A method for manufacturing the fan-out semiconductor package is also disclosed.

公开(公告)号：US20210050275A1

公开(公告)日：2021-02-18

申请号：US16741358

申请日：2020-01-13

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG-CHIEN ,  Hung-Hsin HSU ,  Nan-Chun LIN

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/64 ,  H01L23/00

Abstract: A fan-out semiconductor package and packaging method thereof are disclosed. In the packaging method, a photosensitive material is used to encapsulate multiple bare chips and multiple passive devices, so multiple metal pads of each bare chip and multiple metal terminals of each passive device are exposed out of the photosensitive material by a photolithography process. The exposed metal pads and the exposed metal terminals are directly and electrically connected to a redistribution layer. In the packaging method, the bare chips and the passive devices are located on the same side of the redistribution layer and encapsulated by the photosensitive material. In addition, in the packaging method, the bare chips are not processed by a wafer bump process and does not use the thinner passive devices with high cost. Therefore, a height of the fan-out semiconductor package of the present invention is decreased and a manufacturing cost is relatively reduced.

公开(公告)号：US20220302061A1

公开(公告)日：2022-09-22

申请号：US17392369

申请日：2021-08-03

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu CHANG-CHIEN ,  Hung-Hsin HSU ,  Nan-Chun LIN

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/463 ,  H01L23/488

Abstract: A semiconductor package and fabricating method thereof are disclosed. The semiconductor package has a chip, a plurality of first and second bumps, an encapsulation, a redistribution. The chip has a plurality of pads and an active area and the active surface has a first area and a second area surrounding the first area. The pads are formed on a first area of the active surface. Each first bump is formed on the corresponding pad. The second bumps are formed on the second area and each second bump has a first layer and a second layer with different widths. The encapsulation encapsulates the chip and the first and second bumps and is ground to expose the first and second bumps therefrom. During grinding, all of the first bumps are completely exposed by determining a width of an exposed surface of the second bump to electrically connect to the redistribution is increased.