公开(公告)号：US20210210539A1

公开(公告)日：2021-07-08

申请号：US17134543

申请日：2020-12-28

Applicant: Powertech Technology Inc.

Inventor： Chung-Chang Chang ,  Chang-Lun Lu ,  Ming-Hung Lin

IPC: H01L27/146

Abstract: A sensor includes a first chip, a dam structure and a cover. The first chip includes a substrate, a sensing area and a low-k material layer. The sensing area is located on the surface of the substrate. The low-k material layer is located in the substrate. The dam structure is located on the first chip. The dam structure covers the edge of the low-k material layer. The cover is located on the dam structure and covers the sensing area. A manufacturing method of a sensor is also provided.

公开(公告)号：US11676983B2

公开(公告)日：2023-06-13

申请号：US17134543

申请日：2020-12-28

Applicant: Powertech Technology Inc.

Inventor： Chung-Chang Chang ,  Chang-Lun Lu ,  Ming-Hung Lin

IPC: H01L27/146

CPC classification number: H01L27/14632 ,  H01L27/14618 ,  H01L27/14687

Abstract: A sensor includes a first chip, a dam structure and a cover. The first chip includes a substrate, a sensing area and a low-k material layer. The sensing area is located on the surface of the substrate. The low-k material layer is located in the substrate. The dam structure is located on the first chip. The dam structure covers the edge of the low-k material layer. The cover is located on the dam structure and covers the sensing area. A manufacturing method of a sensor is also provided.

公开(公告)号：US20160099202A1

公开(公告)日：2016-04-07

申请号：US14548307

申请日：2014-11-20

Applicant: Powertech Technology Inc.

Inventor： Ming-Hung Lin

IPC: H01L23/498 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/29099 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83104 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/07802 ,  H01L2924/1515

Abstract: A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer, and a second circuit layer. The base layer has a first surface, a second surface opposite to the first surface, and a recess located on the first surface. The first circuit layer is located on the first surface. The second circuit layer is located on the second surface. The chip is disposed on the first surface and is electrically connected to first circuit layer, where the recess is located on at least one side of the chip. The paste is filled between the chip and the first surface and filled in the recess, where the paste covers a side surface of the chip.

Abstract translation: 提供了包括电路板，芯片和糊料的半导体封装结构。 电路板包括基极层，第一电路层和第二电路层。 基层具有第一表面，与第一表面相对的第二表面和位于第一表面上的凹槽。 第一电路层位于第一表面上。 第二电路层位于第二表面上。 芯片设置在第一表面上并且电连接到第一电路层，其中凹部位于芯片的至少一侧。 糊料填充在芯片和第一表面之间并填充在凹部中，其中糊料覆盖芯片的侧表面。