公开(公告)号：US20190258482A1

公开(公告)日：2019-08-22

申请号：US16265024

申请日：2019-02-01

Applicant: Purdue Research Foundation

Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy

IPC: G06F9/30 ,  G11C11/16 ,  H01L43/08 ,  H01L27/22

Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.

公开(公告)号：US10802827B2

公开(公告)日：2020-10-13

申请号：US16265024

申请日：2019-02-01

Applicant: Purdue Research Foundation

Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy

IPC: G11C11/16 ,  G06F9/30 ,  H01L27/22 ,  H01L43/08 ,  H03K19/18

Abstract: An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.

公开(公告)号：US10825510B2

公开(公告)日：2020-11-03

申请号：US16271811

申请日：2019-02-09

Applicant: Purdue Research Foundation

Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy ,  Indranil Chakraborty

IPC: G11C11/419 ,  G06F17/16 ,  G11C11/412 ,  G11C7/18 ,  G11C7/06

Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

公开(公告)号：US20200258569A1

公开(公告)日：2020-08-13

申请号：US16271811

申请日：2019-02-09

Applicant: Purdue Research Foundation

Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy ,  Indranil Chakraborty

IPC: G11C11/419 ,  G11C11/412 ,  G06F17/16

Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.