公开(公告)号：US20150371695A1

公开(公告)日：2015-12-24

申请号：US14723450

申请日：2015-05-27

Applicant: Purdue Research Foundation

Inventor： Kaushik Roy ,  Dongsoo Lee ,  Xuanyao Fong

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1659

Abstract: An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL0, BL1). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).

Abstract translation: 具有嵌入在STT-MRAM中的ROM的电子数据存储装置。 该装置包括至少两个位线，多个位单元，每个位单元包括连接到源极线（SL）的选择元件（例如，由字线WL栅极控制的晶体管）的串联连接（以任何顺序） 电阻存储元件（例如，MTJ）以及与位线之一（例如，BL0，BL1）的永久连接。 该装置还可以包括ROM读出放大器，其被配置为对连接到相应位线的两个输出节点进行预充电，使得所选择的存储器单元中的跳线将输出节点之一拉到第一参考电位（例如，GND ），并且ROM读出放大器将另一个输出节点拉到第二参考电位（例如，Vdd）。

公开(公告)号：US09552859B2

公开(公告)日：2017-01-24

申请号：US14723450

申请日：2015-05-27

Applicant: Purdue Research Foundation

Inventor： Kaushik Roy ,  Dongsoo Lee ,  Xuanyao Fong

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1659

Abstract: An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL0, BL1). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).

Abstract translation: 具有嵌入在STT-MRAM中的ROM的电子数据存储装置。 该装置包括至少两个位线，多个位单元，每个位单元包括连接到源极线（SL）的选择元件（例如，由字线WL栅极控制的晶体管）的串联连接（以任何顺序） 电阻存储元件（例如，MTJ）以及与位线之一（例如，BL0，BL1）的永久连接。 该装置还可以包括ROM读出放大器，其被配置为对连接到相应位线的两个输出节点进行预充电，使得所选择的存储器单元中的跳线将输出节点之一拉到第一参考电位（例如，GND ），并且ROM读出放大器将另一个输出节点拉到第二参考电位（例如，Vdd）。