公开(公告)号：US20250098323A1

公开(公告)日：2025-03-20

申请号：US18469924

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Ravi Pramod Kumar VEDULA ,  Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: H01L27/13 ,  H01L21/84 ,  H01L23/522

Abstract: An integrated circuit (IC) is described. The IC includes a metal-oxide-metal (MOM) capacitor (MOMCAP). The MOMCAP includes a first terminal coupled to a first plurality of fingers of a first metal interconnect layer. The MOMCAP also includes a second terminal coupled to a second plurality of fingers of the first metal interconnect layer and interdigitated with the first plurality of fingers of the first metal interconnect layer. The IC also includes a first metal-oxide-semiconductor (MOS) capacitor (MOSCAP). The first MOSCAP includes a polysilicon terminal coupled to the first plurality of fingers of the MOMCAP. The first MOSCAP also includes a diffusion terminal coupled to the second plurality of fingers of the MOMCAP.

公开(公告)号：US20210327826A1

公开(公告)日：2021-10-21

申请号：US17002643

申请日：2020-08-25

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/74

Abstract: An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.

公开(公告)号：US20240322791A1

公开(公告)日：2024-09-26

申请号：US18189779

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Jonghae KIM ,  Mishel MATLOUBIAN

IPC: H03H9/17 ,  H03H3/02

CPC classification number: H03H9/173 ,  H03H3/02 ,  H03H2003/021

Abstract: Disclosed are techniques for an integrated circuit (IC) that includes one or more transistors on a substrate and an interconnection structure on the one or more transistors. The interconnection structure includes a semiconductor structure embedded in the interconnection structure. In an aspect, the semiconductor structure includes a cavity structure, a piezoelectric layer over the cavity structure, an upper conductive structure on the piezoelectric layer, and a first contact structure on the upper conductive structure. In an aspect, the cavity structure includes a bottom that is a part of a first etch stop layer over a substrate, a top that is a part of a second etch stop layer over the first etch stop layer, one or more sidewalls connecting the bottom and the top of the cavity structure, and a cavity between the top and the bottom of the cavity structure and surrounded by the one or more sidewalls.

公开(公告)号：US20240321370A1

公开(公告)日：2024-09-26

申请号：US18187993

申请日：2023-03-22

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: G11C17/16 ,  H01L23/525 ,  H10B20/25

CPC classification number: G11C17/165 ,  H01L23/5252 ,  H10B20/25

Abstract: Disclosed are secure anti-fuse one-time programmable (OTP) bit cells. In an aspect, an OTP bit cell includes a P− well comprising an N+ region and a P+ region, a first contact electrically coupled to the N+ region of the P− well, a second contact electrically coupled to the P+ region of the P− well, an insulating layer disposed over a portion of the N+ region, a portion of the P− well, and a portion of the P+ region, a gate structure disposed over the insulating layer, and a third contact electrically coupled to the gate structure. In an unprogrammed mode, the insulating layer creates a high resistance between the third contact and the second contact, and in a programmed mode, a rupture in the insulating layer creates a low resistance between the third contact and the second contact.

公开(公告)号：US20240321369A1

公开(公告)日：2024-09-26

申请号：US18186734

申请日：2023-03-20

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: G11C17/16 ,  G11C17/18 ,  H01L23/525 ,  H10B20/25

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L23/5256 ,  H10B20/25

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a conductive element on an isolation structure, a dielectric film, a first contact structure, wherein at least a portion of the dielectric film is disposed between the conductive element and the first contact structure, and a second contact structure disposed on and electrically coupled with the conductive element. The dielectric film is configured as a resistive element with the first contact structure and the second contact structure being terminals of the resistive element after a dielectric breakdown has occurred within the portion of the dielectric film. Also, the dielectric film is configured as an insulator of a capacitive element with the first contact structure and the second contact structure being terminals of the capacitive element in a case that no dielectric breakdown has occurred within the portion of the dielectric film.

公开(公告)号：US20240319127A1

公开(公告)日：2024-09-26

申请号：US18189494

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Abhijeet PAUL ,  Mishel MATLOUBIAN

IPC: G01N27/22

CPC classification number: G01N27/225 ,  G01N27/228

Abstract: In an aspect, a device includes: a first patterned metal layer; a first dielectric layer disposed over the first patterned metal layer; a second patterned metal layer disposed over the first dielectric layer, wherein the first patterned metal layer, the first dielectric layer, and the second patterned metal layer form a first capacitor; a second moisture-sensitive dielectric layer disposed over the second patterned metal layer; and a third patterned metal layer disposed over the second moisture-sensitive dielectric layer, wherein the third patterned metal layer, the second moisture-sensitive dielectric layer, and the second patterned metal layer form a second capacitor that is moisture-sensitive, and the first patterned metal layer is further configured as a heating element to assist in removing moisture from the second moisture-sensitive dielectric layer of the second capacitor in response to provision of an electrical power to the first patterned metal layer.

公开(公告)号：US20210351192A1

公开(公告)日：2021-11-11

申请号：US16869829

申请日：2020-05-08

Applicant: QUALCOMM Incorporated

Inventor： Mishel MATLOUBIAN ,  Taehun KWON ,  Gang LIN

IPC: H01L27/112 ,  H01L29/78 ,  G11C17/16

Abstract: Certain aspects of the present disclosure generally relate to a one-time programmable (OTP) device including an antifuse device. The antifuse device generally includes a first active region, a second active region, a channel region disposed between the first active region and the second active region, a gate region disposed above the channel region, and a first set of lightly doped drain (LDD) extension regions extending partially across the channel region from the first active region and the second active region and extending into a portion of the channel region underneath the gate region. The first set of LDD extension regions have a same dopant type as the gate region and at least one of the first active region or the second active region.