公开(公告)号：US11158955B2

公开(公告)日：2021-10-26

申请号：US16183116

申请日：2018-11-07

Applicant: RAYTHEON COMPANY

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  Jonathan E. Nufio-Molina ,  Andrew R. Southworth

IPC: H01Q1/52 ,  H01Q21/00 ,  H01P1/04 ,  H01Q13/10 ,  H01Q13/18 ,  H05K1/02 ,  H05K3/40 ,  H01P5/02 ,  H01Q17/00 ,  H01Q1/42 ,  H01Q1/44 ,  B33Y10/00 ,  B33Y70/00 ,  B33Y80/00

Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.

公开(公告)号：US20190269021A1

公开(公告)日：2019-08-29

申请号：US16287260

申请日：2019-02-27

Applicant: RAYTHEON COMPANY

Inventor： Jonathan E. Nufio-Molina ,  Thomas V. Sikina ,  James E. Benedict ,  Andrew R. Southworth ,  Semira M. Azadzoi

IPC: H05K3/46 ,  H05K1/02

Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.

公开(公告)号：US12021306B2

公开(公告)日：2024-06-25

申请号：US17511153

申请日：2021-10-26

Applicant: Raytheon Company

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  Jonathan E. Nufio-Molina ,  Andrew R. Southworth

IPC: H01Q21/00 ,  B33Y10/00 ,  B33Y80/00 ,  H01P1/04 ,  H01P5/02 ,  H01Q1/42 ,  H01Q1/44 ,  H01Q1/52 ,  H01Q13/10 ,  H01Q13/18 ,  H01Q17/00 ,  H05K1/02 ,  H05K3/40

CPC classification number: H01Q21/0087 ,  H01P1/047 ,  H01P5/028 ,  H01Q1/42 ,  H01Q1/44 ,  H01Q1/523 ,  H01Q1/526 ,  H01Q13/10 ,  H01Q13/106 ,  H01Q13/18 ,  H01Q17/001 ,  H01Q17/008 ,  H01Q21/0075 ,  H05K1/0219 ,  H05K3/4038 ,  B33Y10/00 ,  B33Y80/00

Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.

公开(公告)号：US11089687B2

公开(公告)日：2021-08-10

申请号：US16287260

申请日：2019-02-27

Applicant: RAYTHEON COMPANY

Inventor： Jonathan E. Nufio-Molina ,  Thomas V. Sikina ,  James E. Benedict ,  Andrew R. Southworth ,  Semira M. Azadzoi

IPC: H05K1/02 ,  H05K1/16 ,  H01P5/16 ,  H01C7/00 ,  B33Y80/00

Abstract: A method of manufacturing a power divider circuit includes milling a conductive material disposed upon a first substrate to form a signal trace. The signal trace includes a division from a single trace to two arm traces, with each of the two arm traces having a proximal end electrically connected to the single trace and a distal end electrically connected to each of two secondary traces. The method further includes depositing a resistive ink between the two distal ends to form a resistive electrical connection between the two arm traces, bonding a second substrate to the first substrate to substantially encapsulate the traces between the first substrate and the second substrate, and milling through at least one of the first substrate or the second substrate to provide access to at least one of the traces. A signal divider is further disclosed.

公开(公告)号：US11145977B2

公开(公告)日：2021-10-12

申请号：US16441837

申请日：2019-06-14

Applicant: RAYTHEON COMPANY

Inventor： Kevin Wilder ,  Jonathan E. Nufio-Molina ,  Phillip W. Thiessen ,  Thomas V. Sikina ,  James E. Benedict ,  Andrew R. Southworth ,  Erika Klek

IPC: H01Q1/12 ,  H01Q25/00 ,  H01Q21/00 ,  H01P1/04 ,  H01Q3/30 ,  H05K1/02

Abstract: An array includes a support structure configured to support columns of beamformer assemblies, and a plurality of beamformer assemblies supported by the support structure. Each beamformer assembly includes at least one beamformer having at least one first beamformer segment and at least one second beamformer segment configured to interconnect with the first beamformer segment.

公开(公告)号：US20190148828A1

公开(公告)日：2019-05-16

申请号：US16183116

申请日：2018-11-07

Applicant: RAYTHEON COMPANY

Inventor： Thomas V. Sikina ,  John P. Haven ,  James E. Benedict ,  Jonathan E. Nufio-Molina ,  Andrew R. Southworth

IPC: H01Q1/52 ,  H01Q1/44 ,  H01Q1/42 ,  H01Q21/00

Abstract: A low profile array (LPA) includes an antenna element array layer having at least one Faraday wall, and a beamformer circuit layer coupled to the antenna element array layer. The beamformer circuit layer has at least one Faraday wall. The Faraday walls extends between ground planes associated with at least one of the antenna element array layer and the beamformer circuit layer.