公开(公告)号：US20240053970A1

公开(公告)日：2024-02-15

申请号：US18333025

申请日：2023-06-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takao TOI ,  Kengo NISHINO ,  Daigo HAYASHI

IPC: G06F8/41

CPC classification number: G06F8/452

Abstract: When a counter circuit that repeatedly counts a loop variable, an accumulator variable, or the like is configured by a programmable device, a processing delay occurs. The processor comprises an array of programmable logic and at least one dedicated counter circuit for counting variables that are repeatedly modified.

公开(公告)号：US20180374538A1

公开(公告)日：2018-12-27

申请号：US15968331

申请日：2018-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Daigo HAYASHI

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G06F3/0638 ,  G11C5/14 ,  G11C11/419

Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.