公开(公告)号：US20140019726A1

公开(公告)日：2014-01-16

申请号：US13935790

申请日：2013-07-05

Applicant: Renesas Electronics Corporation

Inventor： Takao TOI ,  Taro FUJII ,  Yoshinosuke KATO ,  Toshiro KITAOKA

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/3887 ,  G06F15/7867 ,  G06F17/505 ,  G06F17/5054 ,  Y02D10/12 ,  Y02D10/13

Abstract: A parallel arithmetic device includes a status management section, a plurality of processor elements, and a plurality of switch elements for determining the relation of coupling of each of the processor elements. Each of the processor elements includes an instruction memory for memorizing a plurality of operation instructions corresponding respectively to a plurality of contexts so that an operation instruction corresponding to the context selected by the status management section is read out, and a plurality of arithmetic units for performing arithmetic processes in parallel on a plurality of sets of input data in a manner compliant with the operation instruction read out from the instruction memory.

Abstract translation: 并行算术装置包括状态管理部分，多个处理器元件和用于确定每个处理器元件的耦合关系的多个开关元件。 每个处理器元件包括指令存储器，用于存储分别对应于多个上下文的多个操作指令，从而读取与由状态管理部分选择的上下文相对应的操作指令，以及用于执行的多个运算单元 以符合从指令存储器读出的操作指令的方式并行地在多组输入数据上进行算术处理。

公开(公告)号：US20240053970A1

公开(公告)日：2024-02-15

申请号：US18333025

申请日：2023-06-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takao TOI ,  Kengo NISHINO ,  Daigo HAYASHI

IPC: G06F8/41

CPC classification number: G06F8/452

Abstract: When a counter circuit that repeatedly counts a loop variable, an accumulator variable, or the like is configured by a programmable device, a processing delay occurs. The processor comprises an array of programmable logic and at least one dedicated counter circuit for counting variables that are repeatedly modified.

公开(公告)号：US20220004363A1

公开(公告)日：2022-01-06

申请号：US17358579

申请日：2021-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Katsumi TOGAWA ,  Teruhito TANAKA ,  Takao TOI

IPC: G06F7/544 ,  G06F7/53 ,  G06F17/16

Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

公开(公告)号：US20160162291A1

公开(公告)日：2016-06-09

申请号：US15042527

申请日：2016-02-12

Applicant: Renesas Electronics Corporation

Inventor： Takao TOI ,  Taro FUJII ,  Yoshinosuke KATO ,  Toshiro KITAOKA

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/3887 ,  G06F15/7867 ,  G06F17/505 ,  G06F17/5054 ,  Y02D10/12 ,  Y02D10/13

Abstract: A parallel arithmetic device including a plurality of data wirings disposed in a first direction and a second direction; a plurality of flag wirings corresponding to the data wirings; a plurality of wiring coupling switches disposed each being disposed at respective intersections of the data wirings; and a plurality of processor elements surrounded by the data wirings. A processor element from among the plurality of the processor elements is configured to: perform an arithmetic process on data supplied from a first processor element based on a first flag supplied from the first processor element, the data being supplied on data wiring and the first flag being supplied on flag wiring; output a computation result to a second processor element on data wiring; and output a second flag based on the computation result to the second processor on flag wiring.

Abstract translation: 一种并行运算装置，包括沿第一方向和第二方向设置的多条数据布线; 对应于数据配线的多个标志配线; 多个布线耦合开关，每个布置在数据布线的相应交点处; 以及由数据配线包围的多个处理器元件。 多个处理器元件中的处理器元件被配置为：基于从第一处理器元件提供的第一标志，在数据布线上提供的数据和第一标志，对从第一处理器元件提供的数据执行运算处理 在标志布线上提供; 在数据线上将计算结果输出到第二处理器元件; 并且在标志布线上基于计算结果向第二处理器输出第二标志。

公开(公告)号：US20220129247A1

公开(公告)日：2022-04-28

申请号：US17569135

申请日：2022-01-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

公开(公告)号：US20160371147A1

公开(公告)日：2016-12-22

申请号：US15141687

申请日：2016-04-28

Applicant: Renesas Electronics Corporation

Inventor： Yoshitaka IZAWA ,  Katsumi TOGAWA ,  Takao TOI ,  Taro FUJII

IPC: G06F11/14

CPC classification number: G06F11/142 ,  G06F11/00 ,  G06F11/20 ,  G06F11/202 ,  G06F2201/805 ,  G06F2201/85

Abstract: According to an embodiment, a reconfigurable device 1 includes a configuration information storage memory 12, a state transition management unit 11, and a data path unit 13. When a failure is not detected in either of tiles T1 and T2 provided in the data path unit 13, the state transition management unit 11 selects the configuration information item so that a first processing circuit is configured using the tiles T1 and T2, while when a failure is detected in the tile T2, the state transition management unit 11 selects the configuration information item so that after a first intermediate processing circuit is configured using the tile T1 in which no failure is detected, a second intermediate processing circuit is configured again using the tile T1 in order to achieve the first processing circuit.

Abstract translation: 根据实施例，可重新配置设备1包括配置信息存储器12，状态转换管理单元11和数据路径单元13.当在数据路径单元中提供的片T1和T2中的任一个中未检测到故障时 如图13所示，状态转移管理单元11选择配置信息项，使得使用瓦片T1和T2配置第一处理电路，而当在瓦片T2中检测到故障时，状态转换管理单元11选择配置信息项 使得在使用未检测到故障的瓦片T1配置第一中间处理电路之后，使用瓦片T1再次配置第二中间处理电路，以实现第一处理电路。

公开(公告)号：US20160042099A1

公开(公告)日：2016-02-11

申请号：US14922435

申请日：2015-10-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takao TOI ,  Taro FUJII ,  Noritsugu NAKAMURA

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.

公开(公告)号：US20130346929A1

公开(公告)日：2013-12-26

申请号：US13922945

申请日：2013-06-20

Applicant: Renesas Electronics Corporation

Inventor： Takao TOI ,  Taro FUJII ,  Noritsugu NAKAMURA

IPC: G06F17/50

CPC classification number: G06F17/505

Abstract: A behavioral synthesis apparatus includes a determination unit that determines whether or not a loop description should be converted into a pipeline, and a synthesis unit that performs behavioral synthesis while setting a stricter delay constraint for a loop description that is converted into a pipeline than a loop description that is not converted into a pipeline.

Abstract translation: 一种行为合成装置，包括确定循环描述是否应被转换为流水线的确定单元，以及一个合成单元，该单元执行行为合成，同时为循环描述设置更严格的延迟约束，该循环描述被转换成流水线而不是循环 不转换成管道的说明。

公开(公告)号：US20210117352A1

公开(公告)日：2021-04-22

申请号：US17065169

申请日：2020-10-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Teruhito TANAKA ,  Katsumi TOGAWA ,  Takao TOI

IPC: G06F13/28

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

公开(公告)号：US20190384574A1

公开(公告)日：2019-12-19

申请号：US16410825

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.