公开(公告)号：US20150234661A1

公开(公告)日：2015-08-20

申请号：US14704589

申请日：2015-05-05

Applicant: Renesas Electronics Corporation

Inventor： Hiromichi YAMADA ,  Nobuyasu KANEKAWA ,  Tsutomu YAMADA ,  Kesami HAGIWARA

IPC: G06F9/30 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F9/30145 ,  G06F9/4881 ,  G06F11/1492 ,  G06F11/1497 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/2041 ,  G06F11/3024 ,  G06F11/3404 ,  G06F21/566

Abstract: A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.

Abstract translation: 处理器系统包括执行冗余指令集的第一中央处理单元（CPU） 以及执行所述冗余指令集的第二CPU，其中在所述第二CPU在所述冗余指令集中执行冗余指令之前，所述第一CPU能够执行所述冗余指令集中的n（n为预定整数）冗余指令， 并且其中当在执行所述第一CPU中的所述冗余指令集时发生异常时，所述第一CPU执行所述异常指令作为非冗余指令。

公开(公告)号：US20190087367A1

公开(公告)日：2019-03-21

申请号：US16054784

申请日：2018-08-03

Applicant: Renesas Electronics Corporation

Inventor： Hiromichi YAMADA ,  Akihiro YAMATE ,  Yoichi YUYAMA

IPC: G06F13/24 ,  G06F13/16 ,  G06F13/28

Abstract: Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

公开(公告)号：US20180159540A1

公开(公告)日：2018-06-07

申请号：US15797033

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Hiromichi YAMADA ,  Akihiro YAMATE ,  Hitoshi SUZUKI ,  Yoichi YUYAMA ,  Teppei HIROTSU

IPC: H03K21/40 ,  H03K21/38

CPC classification number: H03K21/406 ,  H03K21/38

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed. A semiconductor device 1 includes a clock oscillator 2, a counter 3 configured to count the number of clocks, a periodic register 4 in which a value corresponding to a period for synchronization is set, a comparison circuit 5 configured to compare the count value in the counter 3 with the set value in the periodic register 4, a match flag register 6 in which a predetermined value is set when the count value coincides with the set value, a match output terminal 7 configured to output the value in the match flag register 6 from the own semiconductor device, a match input terminal 8 to which a value output from another semiconductor device to be synchronized is input, and a reset circuit configured to reset the counter 3 and the match flag register 6 when both the value in the match flag register 6 of the own semiconductor device and the value input to the match input terminal 8 become a predetermined value.

公开(公告)号：US20130254592A1

公开(公告)日：2013-09-26

申请号：US13796304

申请日：2013-03-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiromichi YAMADA ,  Nobuyasu Kanekawa ,  Tsutomu Yamada ,  Kesami Hagiwara

IPC: G06F11/20 ,  G06F9/48

CPC classification number: G06F11/2041 ,  G06F9/4881 ,  G06F11/1492 ,  G06F11/1497 ,  G06F11/1641 ,  G06F11/1691 ,  G06F21/566

Abstract: The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.

Abstract translation: 本发明提供了一种半导体集成电路器件，其在抑制性能劣化的同时实现故障的检测。 在与时钟同步地切换的同时执行多个线程的半导体集成电路装置中，为各线程提供用于执行线程的寄存器。 彼此独立的程序和与线程相同的程序在切换时执行。 在通过多个线程执行相同的程序的情况下，提供用于比较使用与线程相对应地提供的寄存器的执行结果的比较电路。

公开(公告)号：US20130232383A1

公开(公告)日：2013-09-05

申请号：US13856485

申请日：2013-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiromichi YAMADA ,  Kotaro SHIMAMURA ,  Kesami HAGIWARA ,  Yoshikazu KIYOSHIGE ,  Yuichi ISHIGURO

IPC: G06F11/16

CPC classification number: G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

Abstract translation: 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。