公开(公告)号：US20220129247A1

公开(公告)日：2022-04-28

申请号：US17569135

申请日：2022-01-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

公开(公告)号：US20220004363A1

公开(公告)日：2022-01-06

申请号：US17358579

申请日：2021-06-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Katsumi TOGAWA ,  Teruhito TANAKA ,  Takao TOI

IPC: G06F7/544 ,  G06F7/53 ,  G06F17/16

Abstract: A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

公开(公告)号：US20210117352A1

公开(公告)日：2021-04-22

申请号：US17065169

申请日：2020-10-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Teruhito TANAKA ,  Katsumi TOGAWA ,  Takao TOI

IPC: G06F13/28

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

公开(公告)号：US20190384574A1

公开(公告)日：2019-12-19

申请号：US16410825

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Taro FUJII ,  Takao TOI ,  Teruhito TANAKA ,  Katsumi TOGAWA

IPC: G06F7/544 ,  G06F17/16

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.