-
公开(公告)号：US20160352474A1
公开(公告)日：2016-12-01
申请号：US15143299
申请日：2016-04-29
Applicant: Rambus Inc.
Inventor： Jared Zerbe , Pak Shing Chau , William Franklin Stonecypher
CPC classification number: H04L1/244 , G01R31/31703 , G01R31/31713 , G01R31/31716 , G01R31/31717 , G01R31/3183 , G01R31/31855 , G01R31/318577 , G01R31/3187 , G06F11/221 , G06F11/26 , G06F13/423 , G11C29/02 , G11C29/022 , G11C29/025 , G11C29/40 , H04B1/04 , H04B1/16 , H04B3/32 , H04B17/0085 , H04L1/0001 , H04L1/242 , H04L1/243 , H04L5/1438 , H04L25/03885
Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.
-
2.发明申请DRIFT DETECTION IN TIMING SIGNAL FORWARDED FROM MEMORY CONTROLLER TO MEMORY DEVICE 有权从存储器控制器向存储器件转发的定时信号中的DRIFT检测公开(公告)号：US20130111256A1
公开(公告)日：2013-05-02
申请号：US13656498
申请日：2012-10-19
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
IPC: G06F1/06
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/14
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
Abstract translation: 一种存储器系统，其中通过测量在具有低于第一定时的频率的第二定时信号中出现的实际相位延迟来确定在存储器件中用于数据传输的第一定时信号的分配中将发生的定时漂移 并且分布在模拟第一定时信号的分布的至少一部分的漂移特性的一个或多个电路中。 实际的相位延迟在存储器件中确定并提供给存储器控制器，使得用于数据传输的定时信号的相位可以基于所确定的定时漂移来调整。
-
公开(公告)号：US20230409072A1
公开(公告)日：2023-12-21
申请号：US18206867
申请日：2023-06-07
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
CPC classification number: G06F1/08 , H03L7/0995 , H04L7/0008 , H03L7/0814 , H04L7/0033 , H03L7/07 , H04L7/10 , G06F13/1689 , G06F1/10 , G06F13/1673 , Y02D10/00
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US11709525B2
公开(公告)日：2023-07-25
申请号：US17830163
申请日：2022-06-01
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
IPC: G06F1/00 , G06F1/08 , H03L7/099 , H04L7/00 , H03L7/081 , H03L7/07 , H04L7/10 , G06F13/16 , G06F1/10
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/00
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US20210173427A1
公开(公告)日：2021-06-10
申请号：US17102119
申请日：2020-11-23
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
Patent Agency Ranking
公开(公告)号：US11983031B2
公开(公告)日：2024-05-14
申请号：US18206867
申请日：2023-06-07
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/00
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US20200089270A1
公开(公告)日：2020-03-19
申请号：US16566287
申请日：2019-09-10
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US20160161977A1
公开(公告)日：2016-06-09
申请号：US14961077
申请日：2015-12-07
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
CPC classification number: G06F1/08 , G06F1/10 , G06F13/1673 , G06F13/1689 , H03L7/07 , H03L7/0814 , H03L7/0995 , H04L7/0008 , H04L7/0033 , H04L7/10 , Y02D10/14
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
公开(公告)号：US20140333361A1
公开(公告)日：2014-11-13
申请号：US14361575
申请日：2012-11-16
Applicant: Rambus Inc.
Inventor： Pak Shing Chau , Wayne S. Richardson , Jun Kim
CPC classification number: H03K5/1565 , H03K3/012 , H03K3/017
Abstract: Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.
Abstract translation: 在占空比测量电路内产生指示相对于期望占空比的占空比误差的大小和方向的占空比误差矢量，使得能够基于阈值确定是否需要占空比调整，避免功耗调节 在占空比在目标范围内的情况下进行跟踪测量。 当认为有必要进行占空比调整时，由占空比误差矢量表示的占空比误差的大小可以用于实现比例而不是增量占空比调整，从而快速地将时钟占空比返回到目标范围。
-
公开(公告)号：US20220365552A1
公开(公告)日：2022-11-17
申请号：US17830163
申请日：2022-06-01
Applicant: Rambus Inc.
Inventor： Jun Kim , Pak Shing Chau , Wayne S. Richardson
Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
-
-
-
-
-
-
-
-
-
Search Results
23
records
(took 0.011 seconds)
