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公开(公告)号：US20240297565A1
公开(公告)日：2024-09-05
申请号：US18592072
申请日：2024-02-29
Applicant: Renesas Electronics America Inc.
Inventor： Michael Jason HOUSTON , Brian Lee ALLEN
CPC classification number: H02M1/0009 , G06F1/04 , H02M1/32
Abstract: Systems and methods for a cycle-by-cycle current limit event indicator is described. A circuit can include receiving a plurality of signals indicating occurrences of a plurality of overcurrent events over a plurality of clock cycles in a voltage regulator. The circuit can further include generating a latch signal to indicate the occurrences of the plurality of overcurrent events over the plurality of clock cycles. The latch signal can remain latched at high voltage for a number of clock cycles.
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公开(公告)号：US20240297588A1
公开(公告)日：2024-09-05
申请号：US18591596
申请日：2024-02-29
Applicant: Renesas Electronics America Inc.
Inventor： Yashovardhan Rao POTLAPALLI , Brian Lee ALLEN , Mehul Dilip SHAH , Akshat SHENOY , Milind Prakash TILE
CPC classification number: H02M3/1584 , H02M1/0025 , H03K17/063 , H03K2217/0063 , H03K2217/0072
Abstract: Systems and methods for power conversion are described. A power converter can operate under low power mode to supply a first load current from a power management integrated circuit (PMIC). The power converter can transition from low power mode to high power mode by one of activating a tri-state mode of the PMIC prior to activating at least one phase in an external power module and operating PMIC and at least one phase of the external power module simultaneously. The external power module and PMIC can be on separate chips. The power converter can operate under high power mode to supply a second load current from the external power module. The second load current can be greater than the first load current. The power converter can transition from high power mode to low power mode by selectively deactivating phases in the external power module prior to activating the PMIC.
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