公开(公告)号：US20230198508A1

公开(公告)日：2023-06-22

申请号：US17554652

申请日：2021-12-17

Applicant: Renesas Electronics America Inc.

Inventor： Dong-Young CHANG ,  Steven Ernest FINN

IPC: H03K3/017 ,  H03K17/687

CPC classification number: H03K3/017 ,  H03K17/6872

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

公开(公告)号：US20250088182A1

公开(公告)日：2025-03-13

申请号：US18463717

申请日：2023-09-08

Applicant: Renesas Electronics America Inc.

Inventor： Steven Ernest FINN ,  Chan Youn WON ,  Suresh ATLURI

IPC: H03K5/04 ,  H03K17/687

Abstract: Systems and methods for operating a driver circuit are described. In a first region of a transition from an input signal to an output signal, a circuit can control a slew rate of the output signal to a first rate. The first region can terminate prior to the output signal reaching a predefined threshold voltage. In a second region of the transition, the circuit can reduce the slew rate of the output signal to a second rate lower than the first rate. The output signal crosses the predefined threshold voltage in the second region. In a third region of the transition, the circuit can increase the slew rate of the output signal to a third rate greater than the second rate. The transition can complete in the third region. The circuit can output the output signal to drive a transistor in an output drive stage of the driver circuit.

公开(公告)号：US20250070776A1

公开(公告)日：2025-02-27

申请号：US18455436

申请日：2023-08-24

Applicant: Renesas Electronics America Inc.

Inventor： Steven Ernest FINN ,  Preston Blaire SLUDER

IPC: H03K17/687 ,  H03K17/06 ,  H03K19/003

Abstract: Systems and methods for skew compensation in a push-pull driver are described. A device can include a first circuit configured to output a skew measurement of an output driver stage in a driver circuit. The device can further include a second circuit configured to determine a first skew parameter based on the skew measurement and apply a first bias that is dependent on the skew measurement to drive a high-side transistor in the output driver stage. The device can further include a third circuit configured to determine a second skew parameter based on the skew measurement and apply a second bias that is dependent on the skew measurement to drive a low-side transistor in the output driver stage. The first bias and the second bias can be complementary.

公开(公告)号：US20250167788A1

公开(公告)日：2025-05-22

申请号：US18516084

申请日：2023-11-21

Applicant: RENESAS ELECTRONICS AMERICA INC.

Inventor： Dong-Young CHANG ,  Steven Ernest FINN ,  Dominic WingKin YIP

IPC: H03L7/08 ,  H03K3/017 ,  H03K5/00 ,  H03K5/01

Abstract: Systems and methods for calibrating a clock signal are described. A device can include a processer, a circuit and a system duty cycle control (DCC) circuit. The circuit can perform a first phase shift on a clock signal to generate a first phase-shifted signal. The circuit can perform a second phase shift on the clock signal to generate a second phase-shifted signal. The circuit can perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal. The circuit can sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal. The circuit can sample an output clock signal at a time where the first voltage signal and the second voltage signal overlaps. The processor can generate a digital code based on the output clock signal. The system DCC circuit can calibrate the clock signal using the digital code.

公开(公告)号：US20240106421A1

公开(公告)日：2024-03-28

申请号：US18531639

申请日：2023-12-06

Applicant: Renesas Electronics America Inc.

Inventor： Dong-Young CHANG ,  Steven Ernest FINN

IPC: H03K3/017 ,  H03K5/156 ,  H03K7/08 ,  H03K17/687

CPC classification number: H03K3/017 ,  H03K5/1565 ,  H03K7/08 ,  H03K17/6872

Abstract: In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.