公开(公告)号：US11817785B2

公开(公告)日：2023-11-14

申请号：US17084070

申请日：2020-10-29

Applicant: Renesas Electronics America Inc.

Inventor： Vipul Raithatha ,  Rob Cox ,  Allan Warrington ,  Vinod Aravindakshan Lalithambika ,  Michael Jason Houston

IPC: H02M3/158 ,  H02M3/157 ,  H02M1/00

CPC classification number: H02M3/1582 ,  H02M3/157 ,  H02M1/0025

Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

公开(公告)号：US11456668B2

公开(公告)日：2022-09-27

申请号：US17083021

申请日：2020-10-28

Applicant: Renesas Electronics America Inc.

Inventor： Vinod Aravindakshan Lalithambika ,  Allan Warrington ,  Vipul Raithatha

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/32

Abstract: A method of operating a hysteretic synthetic current-mode switching regulator is disclosed. In the switching regulator, PWM pulses (PWM) are generated by a PWM generator (20; FIG. 7) in dependence upon a ramp voltage (VR) which oscillates between upper and lower window voltages (VW+, VW−). The ramp voltage depends on a control voltage (VC) which depends on current (IL) through an inductor (6). The method comprise determining whether a period (T) equal to or greater than a given period (TREFRESH) has elapsed without a PWM pulse being generated, upon a positive determination, causing the ramp voltage to be pulled up to or above the upper window voltage (VW+) for a given duration (ΔT) and when said given duration has elapsed, causing the ramp voltage to decrease until a rising edge of a PWM pulse is generated.

公开(公告)号：US20210135679A1

公开(公告)日：2021-05-06

申请号：US17084070

申请日：2020-10-29

Applicant: Renesas Electronics America Inc.

Inventor： Vipul Raithatha ,  Rob Cox ,  Allan Warrington ,  Vinod Aravindakshan Lalithambika ,  Michael Jason Houston

IPC: H03M1/06 ,  H02M3/158 ,  H02M3/157

Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

公开(公告)号：US20210126537A1

公开(公告)日：2021-04-29

申请号：US17083021

申请日：2020-10-28

Applicant: Renesas Electronics America Inc.

Inventor： Vinod Aravindakshan Lalithambika ,  Allan Warrington ,  Vipul Raithatha

IPC: H02M3/158

Abstract: A method of operating a hysteretic synthetic current-mode switching regulator is disclosed. In the switching regulator, PWM pulses (PWM) are generated by a PWM generator (20; FIG. 7) in dependence upon a ramp voltage (VR) which oscillates between upper and lower window voltages (VW+, VW−). The ramp voltage depends on a control voltage (VC) which depends on current (IL) through an inductor (6). The method comprise determining whether a period (T) equal to or greater than a given period (TREFRESH) has elapsed without a PWM pulse being generated, upon a positive determination, causing the ramp voltage to be pulled up to or above the upper window voltage (VW+) for a given duration (ΔT) and when said given duration has elapsed, causing the ramp voltage to decrease until a rising edge of a PWM pulse is generated.