公开(公告)号：US20240030176A1

公开(公告)日：2024-01-25

申请号：US18112323

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Yong PARK ,  Jeong Hyun Lee ,  Choon Bin Yim

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/13

CPC classification number: H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L21/565 ,  H01L21/561 ,  H01L21/4853 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/13 ,  H01L24/83 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/3201 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/1011 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/29005 ,  H01L2224/83091 ,  H01L2224/83201

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip having solder balls formed on a bottom surface thereof, forming an adhesive layer on a top surface of the semiconductor chip, mounting the semiconductor chip on a first wafer using the solder balls, bonding a second wafer to the first wafer and to the adhesive layer of the semiconductor chip that is mounted on the first wafer, forming a molding layer between the first wafer and the second wafer, and cutting the first wafer, the molding layer and the second wafer.