公开(公告)号：US09304965B2

公开(公告)日：2016-04-05

申请号：US13848622

申请日：2013-03-21

Applicant: Samsung Electronics Co., Ltd ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Jae-Ho Kim ,  Sun-Mi Kim ,  Won Woo Ro ,  Changmin Lee ,  Wonseb Jeong ,  Jin-Won Kim

IPC: G06F15/173 ,  H04L29/08 ,  H04L29/06

CPC classification number: G06F15/173 ,  H04L67/322 ,  H04L69/24

Abstract: According to one embodiment, a scheduling method for load balancing in an electronic device such as a server when performing multiple transcoding operations includes performing a first transcoding operation in order to transmit at least one moving image file to a first terminal. The server receives a request from a second terminal to transmit at least one moving image file while performing the first transcoding. The server performs a second transcoding operation in order to transmit the requested moving image file to the second terminal. The server monitors output frame rates of the first transcoding operation and the second transcoding operation, to control the output frame rates.

Abstract translation: 根据一个实施例，当执行多个代码转换操作时，诸如服务器之类的电子设备中的负载平衡的调度方法包括执行第一代码转换操作，以将至少一个运动图像文件发送到第一终端。 服务器在执行第一代码转换时接收来自第二终端的请求以发送至少一个运动图像文件。 服务器执行第二代码转换操作，以便将请求的运动图像文件发送到第二终端。 服务器监视第一代码转换操作和第二代码转换操作的输出帧速率，以控制输出帧速率。

公开(公告)号：US20240053917A1

公开(公告)日：2024-02-15

申请号：US18492762

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US11741034B2

公开(公告)日：2023-08-29

申请号：US17368981

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heehyun Nam ,  Jeongho Lee ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2213/28

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

公开(公告)号：US11586543B2

公开(公告)日：2023-02-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/00 ,  G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12260116B2

公开(公告)日：2025-03-25

申请号：US18492762

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

公开(公告)号：US11899970B2

公开(公告)日：2024-02-13

申请号：US17742184

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hee Hyun Nam ,  Younggeon Yoo ,  Jeongho Lee ,  Younho Jeon ,  Ipoom Jeong ,  Chanho Yoon

IPC: G06F3/06

CPC classification number: G06F3/0658 ,  G06F3/0611 ,  G06F3/0622 ,  G06F3/0683

Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

公开(公告)号：US20230185717A1

公开(公告)日：2023-06-15

申请号：US18166244

申请日：2023-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho LEE ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/0817 ,  G06F3/06 ,  G06F12/0862

CPC classification number: G06F12/0828 ,  G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.

公开(公告)号：US12248700B2

公开(公告)日：2025-03-11

申请号：US17852022

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeokjun Choe ,  Jeongho Lee ,  Younggeon Yoo ,  Wonseb Jeong

IPC: G06F3/06

Abstract: A storage system includes a host and a storage device. The host includes a host processor and a host memory buffer, wherein the host processor includes a CPU core controlling operation of the host and a cache dedicated for use by the CPU core. The host memory buffer includes a submission queue and a completion queue. The storage device is connected to the host through a link and communicates with the host using a transaction layer packet (TLP). The storage device includes a nonvolatile memory device (NVM) and a storage controller, wherein the host writes a nonvolatile memory express (NVMe) command indicating a destination to the submission queue, and the storage controller reads data from the NVM, directly accesses the cache in response to destination information associated with the destination, and stores the read data in the cache.

公开(公告)号：US11880590B2

公开(公告)日：2024-01-23

申请号：US17837286

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Hongju Kal ,  Won Woo Ro ,  Seokmin Lee ,  Gun Ko

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A data processing system and method for accessing a heterogeneous memory system including a processing unit are provided. The heterogeneous memory system includes a memory module and high bandwidth memory (HBM) including a processing-in-memory (PIM) circuit combined with a memory controller. The memory controller is configured to detect a data array required for an arithmetic operation from a memory module or the HBM by using a border index value when the arithmetic operation is performed by the PIM circuit of the HBM and generate a memory module command set and an HBM command set using physical address spaces respectively designated in the memory module and the HBM.

公开(公告)号：US11822813B2

公开(公告)日：2023-11-21

申请号：US17680773

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseb Jeong ,  Yang Seok Ki ,  Jungmin Seo ,  Beomkyu Shin ,  Sangoak Woo ,  Younggeon Yoo ,  Chanho Yoon ,  Myungjune Jung

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F12/0802 ,  G06F2212/60

Abstract: A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.